共 50 条
- [1] Resiliency Challenges in sub-10nm Technologies [J]. 2015 IEEE 33RD VLSI TEST SYMPOSIUM (VTS), 2015,
- [3] Extension of patterning technologies down to sub-10nm half pitch [J]. ADVANCED ETCH TECHNOLOGY FOR NANOPATTERNING II, 2013, 8685
- [4] New Lithography Technology for Sub-10nm Patterning with Shrinking Organic Material [J]. ALTERNATIVE LITHOGRAPHIC TECHNOLOGIES VI, 2014, 9049
- [5] Towards High Performance Sub-10nm finW Bulk FinFET Technology [J]. 2016 46TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC), 2016, : 131 - 134
- [9] Investigation of Performance Limiting Factors of sub-10nm III-V FinFETs [J]. 2015 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS), 2015, : 105 - 108
- [10] Pushing Multiple Patterning in Sub-10nm: Are We Ready? [J]. 2015 52ND ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2015,