共 50 条
- [2] A register file architecture and compilation scheme for clustered ILP processors EURO-PAR 2002 PARALLEL PROCESSING, PROCEEDINGS, 2002, 2400 : 500 - 511
- [3] Code size efficiency in global scheduling for ILP processors SIXTH ANNUAL WORKSHOP ON INTERACTION BETWEEN COMPILERS AND COMPUTER ARCHITECTURES, PROCEEDINGS, 2002, : 79 - 90
- [4] New code generation algorithm for QueueCore - An embedded processor with high ILP EIGHTH INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED COMPUTING, APPLICATIONS AND TECHNOLOGIES, PROCEEDINGS, 2007, : 185 - 192
- [5] Flexible code generation framework for the design of application specific programmable processors Hardware/Software Codesign - Proceedings of the International Workshop, 1999, : 27 - 31
- [6] A flexible code generation framework for the design of application specific programmable processors PROCEEDINGS OF THE SEVENTH INTERNATIONAL WORKSHOP ON HARDWARE/SOFTWARE CODESIGN (CODES'99), 1999, : 27 - 31
- [7] Code generation for embedded processors 13TH INTERNATIONAL SYMPOSIUM ON SYSTEM SYNTHESIS, PROCEEDINGS, 2000, : 173 - 178
- [8] Code generation for core processors DESIGN AUTOMATION CONFERENCE - PROCEEDINGS 1997, 1997, : 232 - 237
- [9] Compiler-driven cached code compression schemes for embedded ILP processors 32ND ANNUAL INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, (MICRO-32), PROCEEDINGS, 1999, : 82 - 92
- [10] ILP Based Multithreaded Code Generation for Simulink Model IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2014, E97D (12): : 3072 - 3082