A Wide-Range All-Digital Delay-Locked Loop for DDR1-DDR5 Applications

被引：6

作者：

Tsai, Chih-Wei ^{[1
]}

Chiu, Yu-Ting ^{[1
,2
]}

Tu, Yo-Hao ^{[1
,3
]}

Cheng, Kuo-Hsing ^{[1
]}

机构：

[1] Natl Cent Univ, Dept Elect Engn, Taoyuan 32001, Taiwan

[2] Elite Semicond Microelect Technol Inc, Hsinchu 30077, Taiwan

[3] MediaTek Inc, Hsinchu 30078, Taiwan

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2021年 / 29卷 / 10期

关键词：

Delays; Harmonic analysis; Clocks; Jitter; Delay lines; Image edge detection; Synchronization; All-digital delay-locked loop (ADDLL); double data rate (DDR); duty cycle; harmonic locking; synchronous mirror delay (SMD); 256-MB SDRAM; DLL;

D O I：

10.1109/TVLSI.2021.3098171

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A high-speed wide-range all-digital delay-locked loop (ADDLL) suitable for double data rate (DDR1)-DDR5 applications is proposed. The proposed architecture combines the advantages of synchronous mirror delay and delay-locked loop (DLL), which can solve the dynamic tracking problem without requiring a long locking time. In addition, the operating range of the aforementioned architecture is extended through harmonic locking detection and autocalibration technologies. For verification, an experimental chip was fabricated using a 90-nm standard CMOS process with a 1-V power supply. The core area occupies 381 mu m x 234 mu m. The measurement results indicate that the operating range of the proposed ADDLL was from 0.1 to 2.7 GHz, and the peak-to-peak period jitter was less than 5 ps. The output error was less than 1.9%, and the maximum quadrature phase error was 3.61 degrees.

引用

页码：1720 / 1729

页数：10

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