Simulation and implementation of discrete cosine transform for MPEG-4

MPEG video compression is used in digital television set-top boxes, DSS, HDTV, video conferencing, Internet & such applications. The Discrete Cosine Transforms (DCT) are used in MPEG & JPEG compression standards. So the DCT component has stringent timing requirements. The high performance which is required can not be achieved by sequential implementation of algorithm. Consequently, high quality of performance can not be achieved. Hence different optimization techniques to improve the performance of the DCT are discussed here. For DCT, VHDL codes were written in behavioral model for pipelined memory optimization design which reduces the memory requirement and cost of implementation. This design was also implemented on FPGA Spartan3e which occupied approximately 69,468 total equivalent gate count. The FPGA testing was made by using software chip-scope.