A Photonic Interconnection Network for Hardware Accelerator Enabled Utility Computing

被引:0
|
作者
Chen, Cathy [1 ]
Wang, Howard [1 ]
Chan, Johnnie [2 ]
Bergman, Keren [1 ]
机构
[1] Columbia Univ, Dept Elect Engn, 1300 SW Mudd,500 West 120th St, New York, NY 10027 USA
[2] Columbia Univ, Dept Comp Sci, New York, NY 10027 USA
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
High-bandwidth connectivity provided by WDM optical interconnects is an important enabler for delocalized hardware accelerators in utility computing. We validate a proposed architecture with an experiment that leverages optical interconnects to demonstrate error free (BER< 10e-12) active switching and multicasting of FPGA generated and received packets.
引用
收藏
页码:98 / +
页数:2
相关论文
共 50 条
  • [21] PCNNA: A Photonic Convolutional Neural Network Accelerator
    Mehrabian, Armin
    Al-Kabani, Yousra
    Sorger, Volker J.
    El-Gbazawi, Tarek
    2018 31ST IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC), 2018, : 169 - 173
  • [22] On-chip Interconnection Network for Accelerator-Rich Architectures
    Cong, Jason
    Gill, Michael
    Hao, Yuchen
    Reinman, Glenn
    Yuan, Bo
    2015 52ND ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2015,
  • [23] An Efficient Analog Convolutional Neural Network Hardware Accelerator Enabled by a Novel Memoryless Architecture for Insect-Sized Robots
    Dadras, Iman
    Ahmadilivani, Mohammad Hasan
    Banerji, Saoni
    Raik, Jaan
    Abloo, Alvo
    2022 11TH INTERNATIONAL CONFERENCE ON MODERN CIRCUITS AND SYSTEMS TECHNOLOGIES (MOCAST), 2022,
  • [24] Efficient design of hardware-enabled reservoir computing in FPGAs
    Penkovsky, Bogdan
    Larger, Laurent
    Brunner, Daniel
    JOURNAL OF APPLIED PHYSICS, 2018, 124 (16)
  • [25] Modeling and Simulation Environment for Photonic Interconnection Networks in High Performance Computing
    Glick, Madeleine
    Rumley, Sebastien
    Hendry, Robert
    Bergman, Keren
    Dutt, Raj
    2013 15TH INTERNATIONAL CONFERENCE ON TRANSPARENT OPTICAL NETWORKS (ICTON 2013), 2013,
  • [26] Hardware Accelerator Supporting Inhibitory Spiking Neural Network
    Qian, Ping
    Han, Rui
    Xie, Lingdong
    Luo, Wang
    Xu, Huarong
    Li, Songsong
    Zheng, Zhendong
    Computer Engineering and Applications, 2024, 60 (08) : 338 - 347
  • [27] ASIC design of IPSec hardware accelerator for network security
    Ha, CS
    Lee, JH
    Leem, DS
    Park, MS
    Choi, BY
    PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 2004, : 168 - 171
  • [28] Simulation of Hardware Accelerator for Wireless Body Sensor Network
    Swati G. Mavinkattimath
    Rajashri Khanai
    Wireless Personal Communications, 2022, 122 : 477 - 487
  • [29] Simulation of Hardware Accelerator for Wireless Body Sensor Network
    Mavinkattimath, Swati G.
    Khanai, Rajashri
    WIRELESS PERSONAL COMMUNICATIONS, 2021, 122 (1) : 477 - 487
  • [30] Sequence Triggered Hardware Trojan in Neural Network Accelerator
    Liu, Zizhen
    Ye, Jing
    Hu, Xing
    Li, Huawei
    Li, Xiaowei
    Hu, Yu
    2020 IEEE 38TH VLSI TEST SYMPOSIUM (VTS 2020), 2020,