High Performance 14nm SOI FinFET CMOS Technology with 0.0174μm2 embedded DRAM and 15 Levels of Cu Metallization

被引：0

作者：

Lin, C-H. ^{[1
]}

Greene, B. ^{[1
]}

Narasimha, S. ^{[1
]}

Cai, J. ^{[1
]}

Bryant, A. ^{[1
]}

Radens, C. ^{[1
]}

Narayanan, V. ^{[1
]}

Linder, B. ^{[1
]}

Ho, H. ^{[1
]}

Aiyar, A. ^{[1
]}

Alptekin, E. ^{[1
]}

An, J-J. ^{[1
]}

Aquilino, M. ^{[1
]}

Bao, R. ^{[1
]}

Basker, V. ^{[1
]}

Breil, N. ^{[1
]}

Brodsky, M. ^{[1
]}

Chang, W. ^{[1
]}

Clevenger, L. ^{[1
]}

Chidambarrao, D. ^{[1
]}

Christiansen, C. ^{[1
]}

Conklin, D. ^{[1
]}

DeWan, C. ^{[1
]}

Dong, H. ^{[1
]}

Economikos, L. ^{[1
]}

Engel, B. ^{[1
]}

Fang, S. ^{[1
]}

Ferrer, D. ^{[1
]}

Friedman, A. ^{[1
]}

Gabor, A. ^{[1
]}

Guarin, F. ^{[1
]}

Guan, X. ^{[1
]}

Hasanuzzaman, M. ^{[1
]}

Hong, J. ^{[1
]}

Hoyos, D. ^{[1
]}

Jagannathan, B. ^{[1
]}

Jain, S. ^{[1
]}

Jeng, S-J. ^{[1
]}

Johnson, J. ^{[1
]}

Kannan, B. ^{[1
]}

Ke, Y. ^{[1
]}

Khan, B. ^{[1
]}

Kim, B. ^{[1
]}

Koswatta, S. ^{[1
]}

Kumar, A. ^{[1
]}

Kwon, T. ^{[1
]}

Kwon, U. ^{[1
]}

Lanzerotti, L. ^{[1
]}

Lee, H-K ^{[1
]}

Lee, W-H. ^{[1
]}

机构：

[1] IBM Semicond Res & Dev Ctr SRDC, Hopewell Jct, NY 12533 USA

来源：

2014 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2014年

关键词：

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

We present a fully integrated 14nm CMOS technology featuring finFET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs. This SOI finFET architecture is integrated with a 4th generation deep trench embedded DRAM to provide an ultra-dense (0.0174um(2)) memory solution for industry leading ` scale-out' processor design. A broad range of Vts is enabled on chip through a unique dual workfunction process applied to both NFETs and PFETs. This enables simultaneous optimization of both lowVt (HP) and HiVt (LP) devices without reliance on problematic approaches like heavy doping or Lgate modulation to create Vt differentiation. The SOI finFET's excellent subthreshold behavior allows gate length scaling to the sub 20nm regime and superior low Vdd operation. This leads to a substantial (> 35%) performance gain for Vdd similar to 0.8V compared to the HP 22nm planar predecessor technology. At the same time, the exceptional FE/BE reliability enables high Vdd (>1.1V) operation essential to the high single thread performance for processors intended for 'scale-up' enterprise systems. A hierarchical BEOL with 15 levels of copper interconnect delivers both high performance wire-ability as well as effective power supply and clock distribution for very large >600mm(2) SoCs.

引用

页数：3

共 40 条

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