Ultra-high-performance 0.13-μm embedded DRAM technology using TiN/HfO2/TiN/W capacitor and body-slightly-tied SOI

被引：0

作者：

Aoki, Y ^{[1
]}

Ueda, T ^{[1
]}

Shirai, H ^{[1
]}

Sakoh, T ^{[1
]}

Kitamura, T ^{[1
]}

Arai, S ^{[1
]}

Sakao, M ^{[1
]}

Inoue, K ^{[1
]}

Takeuchi, M ^{[1
]}

Sugimura, H ^{[1
]}

Hamada, M ^{[1
]}

Wake, T ^{[1
]}

Naritake, I ^{[1
]}

Iizuka, T ^{[1
]}

Yamamoto, T ^{[1
]}

Ando, K ^{[1
]}

Noda, K ^{[1
]}

机构：

[1] NEC Corp Ltd, ULSI Device Dev Div, Sagamihara, Kanagawa 2291198, Japan

来源：

INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST | 2002年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present an ultra-high-performance 0.13-mum embedded DRAM technology, which improves transistor performance in both logic devices and DRAM cells. Simulation results indicate that the typical random access cycle of a 16-Mbit DRAM core exceeds 570 MHz. The full-metal DRAM structure having a newly developed TiN/HfO2/TiN/W capacitor minimizes aspect ratio of the cylindrical capacitor electrode to reduce contact resistance in logic area. Integration of embedded DRAM with BSTSOI (Body-Slightly-Tied SOI) is also demonstrated, with which the logic performance can be further improved and the DRAM cell area is free from floating-body effects.

引用

页码：831 / 834

页数：4