High Performance 14nm SOI FinFET CMOS Technology with 0.0174μm2 embedded DRAM and 15 Levels of Cu Metallization

被引：0

作者：

Lin, C-H. ^{[1
]}

Greene, B. ^{[1
]}

Narasimha, S. ^{[1
]}

Cai, J. ^{[1
]}

Bryant, A. ^{[1
]}

Radens, C. ^{[1
]}

Narayanan, V. ^{[1
]}

Linder, B. ^{[1
]}

Ho, H. ^{[1
]}

Aiyar, A. ^{[1
]}

Alptekin, E. ^{[1
]}

An, J-J. ^{[1
]}

Aquilino, M. ^{[1
]}

Bao, R. ^{[1
]}

Basker, V. ^{[1
]}

Breil, N. ^{[1
]}

Brodsky, M. ^{[1
]}

Chang, W. ^{[1
]}

Clevenger, L. ^{[1
]}

Chidambarrao, D. ^{[1
]}

Christiansen, C. ^{[1
]}

Conklin, D. ^{[1
]}

DeWan, C. ^{[1
]}

Dong, H. ^{[1
]}

Economikos, L. ^{[1
]}

Engel, B. ^{[1
]}

Fang, S. ^{[1
]}

Ferrer, D. ^{[1
]}

Friedman, A. ^{[1
]}

Gabor, A. ^{[1
]}

Guarin, F. ^{[1
]}

Guan, X. ^{[1
]}

Hasanuzzaman, M. ^{[1
]}

Hong, J. ^{[1
]}

Hoyos, D. ^{[1
]}

Jagannathan, B. ^{[1
]}

Jain, S. ^{[1
]}

Jeng, S-J. ^{[1
]}

Johnson, J. ^{[1
]}

Kannan, B. ^{[1
]}

Ke, Y. ^{[1
]}

Khan, B. ^{[1
]}

Kim, B. ^{[1
]}

Koswatta, S. ^{[1
]}

Kumar, A. ^{[1
]}

Kwon, T. ^{[1
]}

Kwon, U. ^{[1
]}

Lanzerotti, L. ^{[1
]}

Lee, H-K ^{[1
]}

Lee, W-H. ^{[1
]}

机构：

[1] IBM Semicond Res & Dev Ctr SRDC, Hopewell Jct, NY 12533 USA

来源：

2014 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2014年

关键词：

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

We present a fully integrated 14nm CMOS technology featuring finFET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs. This SOI finFET architecture is integrated with a 4th generation deep trench embedded DRAM to provide an ultra-dense (0.0174um(2)) memory solution for industry leading ` scale-out' processor design. A broad range of Vts is enabled on chip through a unique dual workfunction process applied to both NFETs and PFETs. This enables simultaneous optimization of both lowVt (HP) and HiVt (LP) devices without reliance on problematic approaches like heavy doping or Lgate modulation to create Vt differentiation. The SOI finFET's excellent subthreshold behavior allows gate length scaling to the sub 20nm regime and superior low Vdd operation. This leads to a substantial (> 35%) performance gain for Vdd similar to 0.8V compared to the HP 22nm planar predecessor technology. At the same time, the exceptional FE/BE reliability enables high Vdd (>1.1V) operation essential to the high single thread performance for processors intended for 'scale-up' enterprise systems. A hierarchical BEOL with 15 levels of copper interconnect delivers both high performance wire-ability as well as effective power supply and clock distribution for very large >600mm(2) SoCs.

引用

页数：3

共 40 条

[1] Design and Optimization of ESD Lateral NPN Device in 14nm FinFET SOI CMOS Technology
Li, You
Mishra, Rahul
Song, Liyang
Gauthier, Robert
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[2] A 0.127 μm2 high performance 65nm SOI based embedded DRAM for on-processor applications
Wang, G.
Cheng, K.
Ho, H.
Faltermeier, J.
Kong, W.
Kim, H.
Cai, J.
Tanner, C., III
McStay, K.
Balasubramanyam, K.
Pei, C.
Ninomiya, L.
Li, X.
Winstel, K.
Dobuzinsky, D.
Naeem, M.
Zhang, R.
Deschner, R.
Brodsky, M. J.
Allen, S.
Yates, J., III
Feng, Y.
Marchetti, P.
Norris, C.
Casarotto, D.
Benedict, J.
Kniffin, A.
Parise, D.
Khan, B.
Barth, J.
Parries, P.
Kirihata, T.
Norum, J.
Iyer, S. S.
2006 INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2006, : 310 - +
[3] ESD Device Performance Analysis in a 14nm FinFET SOI CMOS Technology: Fin-based versus Planar-based
Li, Junjun
Gauthier, Robert
Li, You
Mishra, Rahul
2014 36TH ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM (EOS/ESD), 2014,
[4] 0.026μm2 High Performance Embedded DRAM in 22nm Technology for Server and SOC Applications
Pei, C.
Wang, G.
Aquilino, M.
Arnold, N.
Chandra, B.
Chang, W.
Chen, X.
Davies, W.
Hawkins, K.
Jaeger, D.
Johnson, J. B.
Kwon, O. -J.
Krishnasamy, R.
Kong, W.
Liu, J.
Li, X.
Messenger, B.
Nelson, E.
Nummy, K.
Onishi, K.
Poindexter, D.
Rombawa, S.
Sheraw, C.
Tzou, T.
Wang, X.
Yin, M.
Freeman, G.
Kirahata, T.
Maciejewski, E.
Norum, J.
Robson, N.
Narasimha, S.
Parries, P.
Agnello, P.
Malik, R.
Iyer, S. S.
2014 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2014,
[5] High Performance 14nm FinFET Technology for Low Power Mobile RF Application
Jeong, Eui-Young
Song, Mingeun
Choi, Ilhyeon
Shin, Huichul
Song, Jinhyeok
Maeng, Wooyeol
Park, Halim
Yoon, Hyunki
Kim, Sungchul
Park, Sunny
You, Bong Ho
Cho, Hag-Ju
An, Young Chang
Lee, S. K.
Kwon, S. D.
Jung, Soon-Moon
2017 SYMPOSIUM ON VLSI TECHNOLOGY, 2017, : T142 - T143
[6] A 0.17μm embedded DRAM technology with 0.23μm2 cell size and advanced CMOS
Wurzer, H
Feldner, K
Graf, W
Curello, G
Faul, J
Weber, D
Kieslich, A
2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2000, : 64 - 65
[7] Three-Dimensional Wafer Stacking using Cu TSV integrated with 45nm high performance SOI-CMOS embedded DRAM technology
Batra, Pooja
LaTulipe, Douglas
Skordas, Spyridon
Winstel, Kevin
Kothandaraman, Chandrasekharan
Himmel, Ben
Maier, Gary
He, Bishan
Gamage, Deepal Wehella
Golz, John
Lin, Wei
Vo, Tuan
Priyadarshini, Deepika
Hubbard, Alex
Cauffman, Kristian
Peethala, Brown
Barth, John
Kirihata, Toshiaki
Graves-Abe, Troy
Robson, Norman
Iyer, Subramanian
2013 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), 2013,
[8] 14nm FinFET Device Boost via 2nd Generation Fins Optimized for High Performance CMOS Applications
Bazizi, E. M.
Banghart, E. K.
Au, B.
Tng, J. H. M.
Benistant, F.
Hu, Y.
He, X.
Zhou, D.
Lo, H-C
Choi, D.
Lee, J. G.
2018 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD 2018), 2018, : 202 - 205
[9] A 0.168μm2/0.11μm2 highly scalable high performance embedded DRAM cell for 90/65-nm logic applications
Wang, G
Parries, P
Khan, B
Liu, J
Otani, Y
Norum, J
Robson, N
Kirihata, T
Iyer, SS
2005 IEEE VLSI-TSA INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY (VLSI-TSA-TECH), PROCEEDINGS OF TECHNICAL PAPERS, 2005, : 31 - 32
[10] A 4GHz, low latency TCAM in 14nm SOI FinFET technology using a high performance Current Sense Amplifier for AC current surge reduction
Fritsch, Alexander
Kugel, Michael
Sautter, Rolf
Wendel, Dieter
Pille, Juergen
Torreiter, Otto
Kalyanasundaram, Shankar
Dobson, Daniel A.
ESSCIRC CONFERENCE 2015 - 41ST EUROPEAN SOLID-STATE CIRCUITS CONFERENCE (ESSCIRC), 2015, : 343 - 346

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