Integration challenges of porous ultra low-k spin-on dielectrics

被引：77
|
作者：
Mosig, K
Jacobs, T
Brennan, K
Rasco, M
Wolf, J
Augur, R
机构：
[1] Infineon Technol, CL CTS RM DIE, D-81730 Munich, Germany
[2] Philips, Eindhoven, Netherlands
[3] Texas Instruments Inc, Dallas, TX USA
[4] Motorola Inc, Austin, TX USA
[5] Intel Corp, Hillsboro, OR 97124 USA
来源：
MICROELECTRONIC ENGINEERING | 2002年 / 64卷 / 1-4期
关键词：
porous dielectrics; ultra low-k materials; spin-on dielectrics; dual damascene;
D O I：
10.1016/S0167-9317(02)00767-0
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In the latest edition of the International Technology Roadmap for Semiconductors (ITRS), the predicted time for the introduction of porous ultra low-k materials with a dielectric constant of 2.2 has slipped significantly against earlier predictions. This is largely due to greater-than-expected problems with the integration of these fragile materials, which generally exhibit weak mechanical properties and low resistance against chemical attack, requiring great care during the integration process. This paper discusses some of the challenges encountered and improvements made at International Sematech and elsewhere regarding the integration of spin-on porous ultra low-k dielectrics into a copper dual damascene process. (C) 2002 Elsevier Science B.V. All rights reserved.
引用
收藏
页码：11 / 24
页数：14
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