On-chip Capacitor Low Dropout Voltage Regulator Implemented in 90nm CMOS Technology Process

被引：0

作者：

Arancon, Isaac Samuel V. ^{[1
]}

Hora, Jefferson A. ^{[1
]}

机构：

[1] MSU Iligan Inst Technol, Dept EECE, Microelect Lab, Iligan, Philippines

来源：

IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS DESIGN, SYSTEMS AND APPLICATIONS (ICEDSA 2012) | 2012年

关键词：

Dropout Voltage; LDO; Line Regulation; Load Regulation; Quiescent Current; Transient Response;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low dropout voltage regulator designed and implemented in 90nm 1P9M 3.3V CMOS technology process is presented in this paper. The design consists mainly of three stages, namely, error amplifier, efficiency boosting circuit and a power stage which utilized a power PMOS. Moreover, the design employs a solution to bulky external capacitors of the present low dropout voltage regulators with an on-chip capacitor. Compensation scheme is also used to provide fast transient and stability. Capacitors used on this design doesn't exceed 13pF, this allows the designer to easily integrate the compensation capacitors within the LDO chip. The designed LDO has an active area of 1.14 mu m(2) and a ground current of 94.2 mu A and a dropout voltage of 250mV. The input voltage is ranged from 2-3.6 volts for loading current of 150mA and the output of 1.75 volts.

引用

页码：221 / 224

页数：4

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