40 Gbit/s master-slave D-type flip-flop in InP DHBT technology

被引:3
|
作者
Kasbari, A [1 ]
André, P [1 ]
Godin, J [1 ]
Konczykowska, A [1 ]
机构
[1] Alcatel R&I, OPTO, F-91461 Marcoussis, France
关键词
D O I
10.1049/el:20020241
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A D-type flip-flop (MS D-FF) fabricated in a self-aligned InP DHBT technology is presented. 40 Gbit/s on-wafer measurements 4 limited by measurement setup) show good rise/fall times, low time jitter. as well as important regenerating capabilities. Some important design aspects are highlighted.
引用
收藏
页码:330 / 331
页数:2
相关论文
共 50 条
  • [21] Design and Analysis of Low-Power and Area-Efficient Master-Slave Flip-Flop
    Krishna, G. Rajesh
    Lorenzo, Rohit
    [J]. IETE JOURNAL OF RESEARCH, 2024,
  • [22] THE RESEARCH OF TERNARY D-TYPE EDGE-TRIGGERED FLIP-FLOP
    吴训威
    陈偕雄
    [J]. Science Bulletin, 1987, (15) : 1060 - 1064
  • [23] THE RESEARCH OF TERNARY D-TYPE EDGE-TRIGGERED FLIP-FLOP
    WU, XW
    CHEN, XI
    [J]. KEXUE TONGBAO, 1987, 32 (15): : 1060 - 1064
  • [24] INTEGRATED BIPOLAR MASTER SLAVE D-FLIP-FLOP WITH MULTIPLEXING CAPABILITY FOR GBIT/S OPERATION
    DERKSEN, RH
    REIN, HM
    VATHKE, J
    [J]. ELECTRONICS LETTERS, 1984, 20 (15) : 628 - 630
  • [25] MSIFF: A radiation-hardened flip-flop via interleaving master-slave stage layout topology
    Song, Ruiqiang
    Shao, Jinjin
    Liang, Bin
    Chi, Yaqing
    Chen, Jianjun
    [J]. IEICE ELECTRONICS EXPRESS, 2020, 17 (04):
  • [26] A D-Type Flip-Flop with Enhanced Timing Using Low Supply Voltage
    Bondoq, Osama
    Abugharbieh, Khaldoon
    Hasan, Abdullah
    [J]. 2020 IEEE CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING (CCECE), 2020,
  • [27] Comparative study of static and dynamic D-type flip-flop circuits using InPHBT's
    Yeo, HS
    Burm, J
    Kim, SI
    Min, BG
    Ju, CW
    [J]. COMPOUND SEMICONDUCTORS 2004, PROCEEDINGS, 2005, 184 : 123 - 126
  • [28] Comparative study of static and dynamic D-type flip-flop circuits using InPHBT's
    Yeo, HS
    Burm, J
    Kim, SI
    Min, BG
    Ju, CW
    [J]. PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 2004, : 352 - 355
  • [29] An analysis of the relationship between IDDQ testability and D-type flip-flop structure
    Miura, Y
    Yamazaki, H
    [J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 1998, E81D (10): : 1072 - 1078
  • [30] PHASE-SEQUENCE DETECTOR BUILT WITH A DUAL D-TYPE FLIP-FLOP
    BLUMIN, A
    [J]. ELECTRONIC DESIGN, 1977, 25 (07) : 106 - 106