Design and Analysis of Low-Power and Area-Efficient Master-Slave Flip-Flop

In this paper, a novel master-slave flip-flop is designed that incorporates 15 transistors and a single-phase clock, employing topological and adaptive coupling methods. The proposed flip-flop circuit (PFC) is more efficient than other logic-structured flip-flops. PFC is designed using a 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology node. Notably, the PFC exhibits an impressive 34.18%, 42.92%, 39.71%, 44.39%, and 46.91% improvement in average power consumption compared to the adaptive data track flip-flop (ADTFF), Hybrid Flip-Flop (HFF),18-transistor single-phase clocked (18TSPC), Logic Structured Reduction Flip-Flop (LSRFF), and Topologically compressed flip-flop (TCFF). It also improved the C to Q delay, power delay product (PDP). Monte Carlo simulations of average power and C to Q delay have been performed for 1000 samples. By reducing the number of PMOS transistors, the total area of the PFC is minimized. PFC operates effectively within a clock frequency range of up to 1 GHz.