Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications

被引：22

作者：

Bao, R. ^{[1
]}

Watanabe, K. ^{[1
]}

Zhang, J. ^{[1
]}

Guo, J. ^{[1
]}

Zhou, H. ^{[1
]}

Gaul, A. ^{[1
]}

Sankarapandian, M. ^{[1
]}

Li, J. ^{[1
]}

Hubbard, A. R. ^{[1
]}

Ega, R. V. ^{[1
]}

Pancharatnam, S. ^{[1
]}

Jamison, P. ^{[1
]}

Wang, M. ^{[1
]}

Loubet, N. ^{[1
]}

Basker, V. ^{[1
]}

Dechene, D. ^{[1
]}

Guo, D. ^{[1
]}

Haran, B. ^{[1
]}

Bu, H. ^{[1
]}

Khare, M. ^{[1
]}

机构：

[1] IBM Semicond Technol Res, Albany, NY 12203 USA

来源：

2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2019年

关键词：

D O I：

10.1109/iedm19573.2019.8993480

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In Nanosheet (NS) device architecture, it is much more challenging than FinFET to develop a suitable multiple threshold voltage (multi-Vt) integration with more restrictive requirement on the dimensions due to the critical dimension scaling and complex structure. In this abstract, we reported an innovative integration scheme to enable volumeless multi-Vt and metal multi-Vt to provide the multi-Vt solutions in NS technology for high performance computing (HPC) and low-power applications. We developed a new volumeless multi-Vt for NS to solve the device geometry constraint and offer more margin and the opportunity for further sheet-to-sheet spacing (Tsus) reduction. Furthermore, metal gate boundary control (MGBC) was developed to enable variable NS widths on the same wafer to satisfy both HPC and low-power applications.

引用

页数：4

共 50 条

[21] Gate Stack Solutions in Gate-First FDSOI Technology to meet High Performance, Low Leakage, VT centering and Reliability Criteria
Weber, O.
Josse, E.
Garros, X.
Rafik, M.
Federspiel, X.
Diouf, C.
Toffoli, A.
Zoll, S.
Gourhant, O.
Joseph, V.
Suarez-Segovia, C.
Domengie, F.
Beugin, V.
Saidi, B.
Gros-Jean, M.
Perreau, P.
Mazurier, J.
Richard, E.
Haond, M.
2016 IEEE SYMPOSIUM ON VLSI TECHNOLOGY, 2016,
[22] A Manufacturable Dual Channel (Si and SiGe) High-K Metal Gate CMOS Technology with Multiple Oxides for High Performance and Low Power Applications
Krishnan, S.
Kwon, U.
Moumen, N.
Stoker, M. W.
Harley, E. C. T.
Bedell, S.
Nair, D.
Greene, B.
Henson, W.
Chowdhury, M.
Prakash, D. P.
Wu, E.
Ioannou, D.
Cartier, E.
Na, M. -H.
Inumiya, S.
Mcstay, K.
Edge, L.
Iijima, R.
Cai, J.
Frank, M.
Hargrove, M.
Guo, D.
Kerber, A.
Jagannathan, H.
Ando, T.
Shepard, J.
Siddiqui, S.
Dai, M.
Bu, H.
Schaeffer, J.
Jaeger, D.
Barla, K.
Wallner, T.
Uchimura, S.
Lee, Y.
Karve, G.
Zafar, S.
Schepis, D.
Wang, Y.
Donaton, R.
Saroop, S.
Montanini, P.
Liang, Y.
Stathis, J.
Carter, R.
Pal, R.
Paruchuri, V.
Yamasaki, H.
Lee, J-H.
2011 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2011,
[23] Strained Si Nanosheet pFET Based on SiC Strain Relaxed Buffer Layer for High Performance and Low Power Logic Applications
Chen, Kun
Yang, Jingwen
Wu, Chunlei
Wang, Chen
Xu, Min
Zhang, David Wei
IEEE ACCESS, 2023, 11 : 65491 - 65495
[24] 22FFL: A High Performance and Ultra Low Power FinFET Technology for Mobile and RF Applications
Sell, B.
Bigwood, B.
Cha, S.
Chen, Z.
Dhage, P.
Fan, P.
Giraud-Carrier, M.
Kar, A.
Karl, E.
Ku, C. -J.
Kumar, R.
Lajoie, T.
Lee, H. -J.
Liu, G.
Liu, S.
Ma, Y.
Mudanai, S.
Nguyen, L.
Paulson, L.
Phoa, K.
Pierce, K.
Roy, A.
Russell, R.
Sandford, J.
Stoeger, J.
Stojanovic, N.
Sultana, A.
Waldemer, J.
Wan, J.
Xu, W.
Young, D.
Zhang, J.
Zhang, Y.
Bai, P.
2017 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2017,
[25] 0.18 mu m CMOS technology for high-performance, low-power, and RF applications
Holloway, TC
Dixit, GA
Grider, DT
Ashburn, SP
Aggarwal, R
Shih, A
Zhang, X
Misium, G
Esquivel, AL
Jain, M
Madan, S
Breedijk, T
Singh, A
Thakar, G
Shinn, G
Riemenschneider, B
OBrien, S
Frystak, D
Kittl, J
Amerasekera, A
Aur, S
Nicollian, P
Aldrich, D
Eklund, B
Appel, A
Bowles, C
Parrill, T
1997 SYMPOSIUM ON VLSI TECHNOLOGY: DIGEST OF TECHNICAL PAPERS, 1997, : 13 - 14
[26] A new 45nm RFSOI Technology Optimized for Low Power, High Performance mmWave Applications
Jain, Sameer H.
Mullapudi, R.
Shanbhag, K.
Ethirajan, T.
Hu, Y.
Li, Y.
Chowdhury, T.
Srinivasan, P.
Das, I
Gonzales, O. H.
Kaueraur, T.
Al-Husseini, Z.
Kakar, H. K.
Bantupalli, K.
Lee, J.
Lin, T-Y
Veeramani, E.
Kamineni, H.
Kook, S-Y
Vanukuru, V.
Jain, V
Aravamudhan, D.
Syed, S.
Letavic, T.
Costa, J.
2024 19TH EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE, EUMIC 2024, 2024, : 102 - 105
[27] Technology and design challenges for low power and high performance microprocessors
De, V
Borkar, S
ADVANCED METALLIZATION CONFERENCE 2000 (AMC 2000), 2001, : 25 - 34
[28] Design of TCAM Architecture for Low Power and High Performance Applications
Veera Venkata Satyanarayana, Satti
Sriadibhatla, Sridevi
GAZI UNIVERSITY JOURNAL OF SCIENCE, 2019, 32 (01): : 164 - 173
[29] Design of High Performance Binary Circuits for Low Power Applications
Kathirvelu, M.
Rajendran, A.
BIOSCIENCE BIOTECHNOLOGY RESEARCH COMMUNICATIONS, 2020, 13 (06): : 131 - 135
[30] Low power optoelectronic modules for high performance switching applications
Guilfoyle, PS
McCallum, DS
Hessenbruch, JM
Stone, RV
Kim, JW
1997 IEEE AEROSPACE CONFERENCE PROCEEDINGS, VOL 3, 1997, : 211 - 234

← 1 2 3 4 5 →