Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications

被引：22

作者：

Bao, R. ^{[1
]}

Watanabe, K. ^{[1
]}

Zhang, J. ^{[1
]}

Guo, J. ^{[1
]}

Zhou, H. ^{[1
]}

Gaul, A. ^{[1
]}

Sankarapandian, M. ^{[1
]}

Li, J. ^{[1
]}

Hubbard, A. R. ^{[1
]}

Ega, R. V. ^{[1
]}

Pancharatnam, S. ^{[1
]}

Jamison, P. ^{[1
]}

Wang, M. ^{[1
]}

Loubet, N. ^{[1
]}

Basker, V. ^{[1
]}

Dechene, D. ^{[1
]}

Guo, D. ^{[1
]}

Haran, B. ^{[1
]}

Bu, H. ^{[1
]}

Khare, M. ^{[1
]}

机构：

[1] IBM Semicond Technol Res, Albany, NY 12203 USA

来源：

2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2019年

关键词：

D O I：

10.1109/iedm19573.2019.8993480

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In Nanosheet (NS) device architecture, it is much more challenging than FinFET to develop a suitable multiple threshold voltage (multi-Vt) integration with more restrictive requirement on the dimensions due to the critical dimension scaling and complex structure. In this abstract, we reported an innovative integration scheme to enable volumeless multi-Vt and metal multi-Vt to provide the multi-Vt solutions in NS technology for high performance computing (HPC) and low-power applications. We developed a new volumeless multi-Vt for NS to solve the device geometry constraint and offer more margin and the opportunity for further sheet-to-sheet spacing (Tsus) reduction. Furthermore, metal gate boundary control (MGBC) was developed to enable variable NS widths on the same wafer to satisfy both HPC and low-power applications.

引用

页数：4

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