Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications

被引：22

作者：

Bao, R. ^{[1
]}

Watanabe, K. ^{[1
]}

Zhang, J. ^{[1
]}

Guo, J. ^{[1
]}

Zhou, H. ^{[1
]}

Gaul, A. ^{[1
]}

Sankarapandian, M. ^{[1
]}

Li, J. ^{[1
]}

Hubbard, A. R. ^{[1
]}

Ega, R. V. ^{[1
]}

Pancharatnam, S. ^{[1
]}

Jamison, P. ^{[1
]}

Wang, M. ^{[1
]}

Loubet, N. ^{[1
]}

Basker, V. ^{[1
]}

Dechene, D. ^{[1
]}

Guo, D. ^{[1
]}

Haran, B. ^{[1
]}

Bu, H. ^{[1
]}

Khare, M. ^{[1
]}

机构：

[1] IBM Semicond Technol Res, Albany, NY 12203 USA

来源：

2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2019年

关键词：

D O I：

10.1109/iedm19573.2019.8993480

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In Nanosheet (NS) device architecture, it is much more challenging than FinFET to develop a suitable multiple threshold voltage (multi-Vt) integration with more restrictive requirement on the dimensions due to the critical dimension scaling and complex structure. In this abstract, we reported an innovative integration scheme to enable volumeless multi-Vt and metal multi-Vt to provide the multi-Vt solutions in NS technology for high performance computing (HPC) and low-power applications. We developed a new volumeless multi-Vt for NS to solve the device geometry constraint and offer more margin and the opportunity for further sheet-to-sheet spacing (Tsus) reduction. Furthermore, metal gate boundary control (MGBC) was developed to enable variable NS widths on the same wafer to satisfy both HPC and low-power applications.

引用

页数：4

共 50 条

[1] Sensitivity-based multiple-Vt cell swapping for leakage power reduction
Lee, Wan-Ping
Liu, Hung-Yi
Ho, Kuan-Hsien
Chang, Yao-Wen
2008 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM, 2008, : 168 - 171
[2] Capping-Metal Gate Integration Technology for multiple-VT CMOS in MuGFETs
Veloso, A.
Witters, L.
Demand, M.
Ferain, I.
Son, N. J.
Kaczer, B.
Roussel, Ph. J.
Adelmann, C.
Brus, S.
Richard, O.
Bender, H.
Conard, T.
Vos, R.
Rooyackers, R.
Van Elshocht, S.
Collaert, N.
De Meyer, K.
Biesemans, S.
Jurczak, M.
2008 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2008, : 119 - +
[3] Enabling Multiple-Vt Device Scaling for CMOS Technology beyond 7nm Node
Chang, Vincent S.
Wang, S. H.
Lu, J. H.
Wu, W. H.
Wu, B. F.
Hsu, B. C.
Kwong, K. C.
Yeh, J. Y.
Chang, C. H.
Chen, C. H.
Chui, C. O.
Yeh, M. S.
Huang, K. B.
Chen, R.
Chen, K. S.
Wu, S. Y.
2020 IEEE SYMPOSIUM ON VLSI TECHNOLOGY, 2020,
[4] Si FinFET based 10nm Technology with Multi Vt Gate Stack for Low Power and High Performance Applications
Cho, H. -J.
Oh, H. S.
Nam, K. J.
Kim, Y. H.
Yeo, K. H.
Kim, W. D.
Chung, Y. S.
Nam, Y. S.
Kim, S. M.
Kwon, W. H.
Kang, M. J.
Kim, I. R.
Fukutome, H.
Jeong, C. W.
Shin, H. J.
Kim, Y. S.
Kim, D. W.
Park, S. H.
Oh, H. S.
Jeong, J. H.
Kim, S. B.
Ha, D. W.
Park, J. H.
Rhee, H. S.
Hyun, S. J.
Shin, D. S.
Kim, D. H.
Kim, H. Y.
Maeda, S.
Lee, K. H.
Kim, Y. H.
Kim, M. C.
Koh, Y. S.
Yoon, B.
Shin, K.
Lee, N. I.
Kangh, S. B.
Hwang, K. H.
Lee, J. H.
Ku, J. -H.
Nam, S. W.
Jung, S. M.
Kang, H. K.
Yoon, J. S.
Jung, E. S.
2016 IEEE SYMPOSIUM ON VLSI TECHNOLOGY, 2016,
[5] Flexible and robust capping-metal gate integration technology enabling multiple-VT CMOS in MuGFETs
Veloso, A.
Witters, L.
Demand, M.
Ferain, I.
Son, N. J.
Kaczer, B.
Roussel, Ph. J.
Simoen, E.
Kauerauf, T.
Adelmann, C.
Bras, S.
Richard, O.
Bender, H.
Conard, T.
Vos, R.
Rooyackers, R.
Van Elshocht, S.
Collaert, N.
De Meyer, K.
Biesemans, S.
Jurczak, M.
2008 SYMPOSIUM ON VLSI TECHNOLOGY, 2008, : 11 - +
[6] LTCC technology for high performance low power base station applications
Passiopoulos, G
CERAMIC INTERCONNECT TECHNOLOGY: NEXT GENERATION, 2003, 5231 : 85 - 90
[7] High performance low power VT-wave-pipeline CMOS circuit in PD/SOI technology
Joshi, RV
Yee, F
Kim, K
Williams, RQ
Chuang, CT
2002 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2002, : 128 - 129
[8] Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
Zhang, J.
Frougier, J.
Greene, A.
Miao, X.
Yu, L.
Vega, R.
Montanini, P.
Durfee, C.
Gaul, A.
Pancharatnam, S.
Adams, C.
Wu, H.
Zhou, H.
Shen, T.
Xie, R.
Sankarapandian, M.
Wang, J.
Watanabe, K.
Bao, R.
Liu, X.
Park, C.
Shobha, H.
Joseph, P.
Kong, D.
De La Pena, A. Arceo
Li, J.
Conti, R.
Dechene, D.
Loubet, N.
Chao, R.
Yamashita, T.
Robison, R.
Basker, V.
Zhao, K.
Guo, D.
Haran, B.
Divakaruni, R.
Bu, H.
2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2019,
[9] 10nm FINFET Technology for Low Power and High Performance Applications
Guo, D.
Shang, H.
Seo, K.
Haran, B.
Standaert, T.
Gupta, D.
Alptekin, E.
Bae, D.
Bae, G.
Chanemougame, D.
Cheng, K.
Cho, J.
Hamieh, B.
Hong, J.
Hook, T.
Jung, J.
Kambhampati, R.
Kim, B.
Kim, H.
Kim, K.
Kim, T.
Liu, D.
Mallela, H.
Montanini, P.
Mottura, M.
Nam, S.
Ok, L.
Park, Y.
Paul, A.
Prindle, C.
Ramachandran, R.
Sardesai, V.
Scholze, A.
Seo, S.
Southwick, R.
Strane, J.
Sun, X.
Tsutsui, G.
Tripathi, N.
Vega, R.
Weybright, M.
Xie, R.
Yeh, C.
Bu, H.
Burns, S.
Canaperi, D.
Celik, M.
Colburn, M.
Jagannathan, H.
Kanakasabaphthy, S.
2014 12TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2014,
[10] Synthesis of low power high performance dual-VT PTL circuits
Samanta, D
Pal, A
17TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: DESIGN METHODOLOGIES FOR THE GIGASCALE ERA, 2004, : 85 - 90

← 1 2 3 4 5 →