3-D thermal modeling of FinFET

被引：0

作者：

Joshi, RV ^{[1
]}

Pascual-Gutiérrez, JA ^{[1
]}

Chuang, CT ^{[1
]}

机构：

[1] IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA

来源：

PROCEEDINGS OF ESSDERC 2005: 35TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2005年

关键词：

D O I：

10.1109/ESSDER.2005.1546589

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents three-dimensional thermal simulations using Fourier's law for multi-finger FinFET devices at 90 nm, 65 nm, and 45 nm technology nodes using measured/extracted thermal resistance of thin Si film from real nanoscale devices for the first time. It is shown that the thermal resistance of thin Si film in the channel region increases (by factor of 3-4) compared to bulk due to phonon boundary scattering and phonon confinement. The simulation results are discussed and compared with homologous single-gate devices to conclude the graver thermal challenges FinFETs pose in the design of integrated circuits.

引用

页码：77 / 80

页数：4

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