3-D thermal modeling of FinFET

This paper presents three-dimensional thermal simulations using Fourier's law for multi-finger FinFET devices at 90 nm, 65 nm, and 45 nm technology nodes using measured/extracted thermal resistance of thin Si film from real nanoscale devices for the first time. It is shown that the thermal resistance of thin Si film in the channel region increases (by factor of 3-4) compared to bulk due to phonon boundary scattering and phonon confinement. The simulation results are discussed and compared with homologous single-gate devices to conclude the graver thermal challenges FinFETs pose in the design of integrated circuits.