Dual threshold voltage and sleep switch dual threshold voltage DOIND approach for leakage reduction in domino logic circuits

Subthreshold leakage current becomes the major component of total power dissipation as scaling down the feature size. In this paper, two new circuit techniques are proposed for reducing the subthreshold leakage power consumption in domino logic circuit. Dual threshold voltage DOIND (Domino logic with clock and input dependent transistors) and NMOS sleep switch dual threshold voltage DOIND circuits for low leakage domino logic circuits are presented. High threshold voltage transistors are utilized to reduce the leakage current and a sleep transistor is added to the dynamic node that strongly turnoff all the high threshold voltage transistor and significantly reduce the subthreshold leakage power. The proposed circuit techniques, dual threshold voltage DOIND logic and sleep switch dual threshold voltage DOIND logic reduces the leakage current by 71.46 and 74.86% respectively as compared to standard domino logic circuit. Simulation results also shows that both the circuits are less affected by supply and temperature variations. The proposed sleep switch dual threshold voltage DOIND exhibits 19.95% less power consumption with 24% die area overhead for the buffer circuit as compared to standard domino logic circuit. The proposed sleep switch dual threshold voltage DOIND logic has improved normalized figure of merit of 1.17 as compared to standard domino logic circuit.