Research and Design of AVS Video Decoder Bit Rate Control

被引：0

作者：

Xiong, Jiang ^{[1
]}

Yi, Qingming ^{[1
]}

Shi, Min ^{[1
]}

机构：

[1] Jinan Univ, Act Jinan Univ Integrated Circuit Design Joint La, Guangzhou 510632, Guangdong, Peoples R China

来源：

ADVANCES IN ENERGY SCIENCE AND TECHNOLOGY, PTS 1-4 | 2013年 / 291-294卷

关键词：

bit rate; decoder; AVS; hardware;

D O I：

10.4028/www.scientific.net/AMM.291-294.2913

中图分类号：

TE [石油、天然气工业]; TK [能源与动力工程];

学科分类号：

0807 ; 0820 ;

摘要：

In common video compression coding technology, data with changing bit rate is not suitable for transmission in fixed bit rate channel. A bit rate control algorithm and a hardware design suitable for AVS decoder are proposed in this paper. The target bits are calculated and allocated in three levels, including GOP, frame and MB. The proposed hardware design passes the simulation verification. The result of synthesis in DC proves that the design meets timing requirements. The design is easy to realize and suitable for controlling the bit rate in real-time encoding.

引用

页码：2913 / 2916

页数：4

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