A 20-GHz phase-locked loop for 40-Gb/s serializing transmitter in 0.13-μm CMOS

被引：35
|
作者：
Kim, J [1 ]
Kim, JK [1 ]
Lee, BJ [1 ]
Kim, N [1 ]
Jeong, DK [1 ]
Kim, W [1 ]
机构：
[1] Seoul Natl Univ, Seoul 151742, South Korea
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2006年 / 41卷 / 04期
关键词：
CMOS frequency divider; phase-locked loop (PLL); pulsed latch; reference spur; VCO optimization;
D O I：
10.1109/JSSC.2006.870766
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 20-GHz phase-locked loop with 4.9 ps(pp)/0.65 ps(rms) jitter and -113.5 dBc/Hz phase noise at 10-MHz offset is presented. A half-duty sampled-feed forward loop filter that simply replaces the resistor with a switch and an inverter suppresses the reference spur down to -44.0 dBc. A design iteration procedure is outlined that minimizes the phase noise of a negative-g(m) oscillator with a coupled microstrip resonator. Static frequency dividers made of pulsed latches operate faster than those made of Hip-flops and achieve near 2:1 frequency range. The phase-locked loop fabricated in a 0.13-mu m CMOS operates from 17.6 to 19.4 GHz and dissipates 480 mW.
引用
收藏
页码：899 / 908
页数：10
相关论文
共 50 条
  • [1] A 20-GHz phase-locked loop for 40Gb/s serializing transmitter in 0.13μm CMOS
    Kim, J
    Kim, JK
    Lee, BJ
    Kim, N
    Jeong, DK
    Kim, W
    [J]. 2005 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2005, : 144 - 147
  • [2] A 50-GHz phase-locked loop in 0.13-μm CMOS
    Cao, Changhua
    Ding, Yanping
    Kenneth, K. O.
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2007, 42 (08) : 1649 - 1656
  • [3] A 40-Gb/s transceiver in 0.13-μm CMOS technology
    Kim, Jeong-Kyoum
    Kim, Jaeha
    Kim, Gyudong
    Chi, Hankyu
    Jeong, Deog-Kyoon
    [J]. 2008 IEEE SYMPOSIUM ON VLSI CIRCUITS, 2008, : 153 - +
  • [4] A 40-Gb/s transceiver in 0.13-μm CMOS technology
    Kim, Jeong-Kyoum
    Kim, Jaeha
    Kim, Gyudong
    Chi, Hankyu
    Jeong, Deog-Kyoon
    [J]. 2008 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2008, : 196 - +
  • [5] An 18.7mW 10-GHz Phase-Locked Loop Circuit in 0.13-μm CMOS
    Tseng, I-Wei
    Wu, Jen-Ming
    [J]. 2009 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM, 2009, : 227 - 230
  • [6] A low spur,low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology
    梅年松
    孙瑜
    陆波
    潘姚华
    黄煜梅
    洪志良
    [J]. Journal of Semiconductors, 2011, 32 (03) : 100 - 104
  • [7] Design Optimization of On-Chip Inductive Peaking Structures for 0.13-μm CMOS 40-Gb/s Transmitter Circuits
    Kim, Jaeha
    Kim, Jeong-Kyoum
    Lee, Bong-Joon
    Jeong, Deog-Kyoon
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2009, 56 (12) : 2544 - 2555
  • [8] A Fully Integrated 0.13-μm CMOS 40-Gb/s Serial Link Transceiver
    Kim, Jeong-Kyoum
    Kim, Jaeha
    Kim, Gyudong
    Jeong, Deog-Kyoon
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2009, 44 (05) : 1510 - 1521
  • [9] A 4224 MHz low jitter phase-locked loop in 0.13-μm CMOS technology
    陈虎
    陆波
    邵轲
    夏玲琍
    黄煜梅
    洪志良
    [J]. Journal of Semiconductors, 2010, (01) : 46 - 50
  • [10] A 5-GHz Fractional-N Phase-Locked Loop With Spur Reduction Technique in 0.13-μm CMOS
    Chiu, Wei-Hao
    Cheng, Chien-Yuan
    Lin, Tsung-Hsien
    [J]. 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 2996 - 2999
12345