A 20-GHz phase-locked loop for 40-Gb/s serializing transmitter in 0.13-μm CMOS

被引：35

作者：

Kim, J ^{[1
]}

Kim, JK ^{[1
]}

Lee, BJ ^{[1
]}

Kim, N ^{[1
]}

Jeong, DK ^{[1
]}

Kim, W ^{[1
]}

机构：

[1] Seoul Natl Univ, Seoul 151742, South Korea

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2006年 / 41卷 / 04期

关键词：

CMOS frequency divider; phase-locked loop (PLL); pulsed latch; reference spur; VCO optimization;

D O I：

10.1109/JSSC.2006.870766

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 20-GHz phase-locked loop with 4.9 ps(pp)/0.65 ps(rms) jitter and -113.5 dBc/Hz phase noise at 10-MHz offset is presented. A half-duty sampled-feed forward loop filter that simply replaces the resistor with a switch and an inverter suppresses the reference spur down to -44.0 dBc. A design iteration procedure is outlined that minimizes the phase noise of a negative-g(m) oscillator with a coupled microstrip resonator. Static frequency dividers made of pulsed latches operate faster than those made of Hip-flops and achieve near 2:1 frequency range. The phase-locked loop fabricated in a 0.13-mu m CMOS operates from 17.6 to 19.4 GHz and dissipates 480 mW.

引用

页码：899 / 908

页数：10

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