A 40-Gb/s transceiver in 0.13-μm CMOS technology

被引：10

作者：

Kim, Jeong-Kyoum ^{[1
]}

Kim, Jaeha ^{[3
]}

Kim, Gyudong ^{[2
]}

Chi, Hankyu ^{[1
]}

Jeong, Deog-Kyoon ^{[1
]}

机构：

[1] Seoul Natl Univ, Seoul, South Korea

[2] Silicon Image, Sunnyvale, CA USA

[3] Rambus Inc, Los Altos, CA USA

来源：

2008 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2008年

关键词：

D O I：

10.1109/VLSIC.2008.4586004

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A fully integrated 40-Gb/s transceiver is implemented in a 0.13-mu m CMOS technology. This paper describes the challenges in designing a 20-GHz input sampler, a 20-GHz quadrature LC-VCO, a 20-GHz bang-bang phase detector, and a 40-Gb/s equalizer. The transceiver occupies 1.7 x 2.9mm(2) and dissipates 3.6W from a 1.45-V supply. With the equalizer on, the transmit jitter of the 39-Gb/s 2(15)-1 PRBS data is 1.85ps(rms) over a wire-bonded plastic ball grid array (PBGA) package, an 8-mm RO-4350B PCB trace, an on-board 2.4-mm connector, and a 1m-long 2.4-mm coaxial cable, while the recovered clock jitter is 1.77 ps(rms). The measured BER is < 10(-14).

引用

页码：196 / +

页数：2

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