Enhanced BIST-based diagnosis of FPGAs via Boundary Scan access

被引：14
|
作者：
Hamilton, C [1 ]
Gibson, G [1 ]
Wijesuriya, S [1 ]
Stroud, C [1 ]
机构：
[1] Univ Kentucky, Lexington, KY 40506 USA
来源：
17TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 1999年
关键词：
D O I：
10.1109/VTEST.1999.766697
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Four methods for accessing BIST for FPGAs via the IEEE 1149.1 standard Boundary Scan interface are presented and discussed in terms of advantages/disadvantages including their impact on test time and diagnostic resolution. These methods can be used in a variety of FPGA architectures for system level testing and diagnosis.(1).
引用
收藏
页码：413 / 418
页数：4
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