共 50 条
- [1] Enhanced BIST-based diagnosis of FPGAs via Boundary Scan access [J]. 17TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1999, : 413 - 418
- [2] BIST-based delay-fault testing in FPGAs [J]. PROCEEDINGS OF THE EIGHTH IEEE INTERNATIONAL ON-LINE TESTING WORKSHOP, 2002, : 131 - 134
- [3] BIST-based delay-fault testing in FPGAs [J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2003, 19 (05): : 549 - 558
- [4] BIST-Based Delay-Fault Testing in FPGAs [J]. Journal of Electronic Testing, 2003, 19 : 549 - 558
- [5] BIST-based diagnosis of FPGA interconnect [J]. INTERNATIONAL TEST CONFERENCE 2002, PROCEEDINGS, 2002, : 618 - 627
- [6] BIST-based diagnosis scheme for field programmable gate array interconnect delay faults [J]. IET COMPUTERS AND DIGITAL TECHNIQUES, 2007, 1 (06): : 716 - 723
- [7] BIST-based online test approach for SRAM-based FPGAs [J]. 26TH IRANIAN CONFERENCE ON ELECTRICAL ENGINEERING (ICEE 2018), 2018, : 178 - 183
- [9] BIST-based fault diagnosis in the presence of embedded memories [J]. INTERNATIONAL CONFERENCE ON COMPUTER DESIGN - VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 1997, : 37 - 47
- [10] BIST-based fault diagnosis in the presence of embedded memories [J]. VLSI DESIGN, 2001, 12 (04) : 487 - 500