10-Gb/s BM-CDR Circuit With Synchronous Data Output for Optical Networks

被引：6

作者：

Yu, Runxiang ^{[1
]}

Proietti, Roberto ^{[1
]}

Yin, Shuang ^{[1
]}

Kurumida, Junya ^{[2
]}

Ben Yoo, S. J. ^{[1
]}

机构：

[1] Univ Calif Davis, Dept Elect & Comp Engn, Davis, CA 95616 USA

[2] Natl Inst Adv Ind Sci & Technol, NPRC, Tsukuba 3058568, Japan

来源：

IEEE PHOTONICS TECHNOLOGY LETTERS | 2013年 / 25卷 / 05期

关键词：

Bit synchronization; burst mode; clock and data recovery; multiphase clock; BURST-MODE CLOCK;

D O I：

10.1109/LPT.2013.2242461

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This letter presents a 10-Gb/s burst-mode clock and data recovery (BM-CDR) circuit based on an analog phase-picking method. The experiment demonstrates that the proposed BM-CDR circuit is able to align the BM data to a local clock with a phase alignment accuracy of +/-pi/4, a 25-ns latency and zero bit loss. The circuit further resamples the aligned data using the local clock for jitter reduction. The experiment shows error-free operation of the BM-CDR circuit for burst-mode data packets with various phase delays.

引用

页码：508 / 511

页数：4

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