Multi-Histogram ADC BIST System for ADC Linearity Testing

被引：4

作者：

Chan, Koay Soon ^{[1
]}

Nordin, Nuzrul Fahmi ^{[1
]}

Chan, Kim Chon ^{[1
]}

Lok, Terk Zyou ^{[1
]}

Yong, Chee Wai ^{[1
]}

机构：

[1] Marvell Semicond Sdn Bhd, George Town, Malaysia

来源：

2013 22ND ASIAN TEST SYMPOSIUM (ATS) | 2013年

关键词：

Built-in Self-test; ADC BIST; ADC linearity test; Histogram testing; Triangle wave;

D O I：

10.1109/ATS.2013.47

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes an ADC BIST system that utilizes a modified linear ramp histogram approach to test the linearity of an ADC with 10 bits of resolution on a System-On-Chip (SoC). The system tests the differential non-linearity (DNL) and Integral Non-linearity (INL) of an ADC. The ADC is tested in sections using a small amplitude triangle wave which is generated by charging and discharging an on-chip capacitor. This is an alternative solution to test an ADC when ADC-DAC loopback testing is not feasible. Both the ADC and BIST are designed in the 40nm process node. Simulation results show that the BIST is capable of testing a 10-bit ADC.

引用

页码：213 / 214

页数：2

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