A Fast Partitioning Algorithm on the 3D Network on Chip Architecture for the Signal Processing Application

With the growing complexity in consumer embedded systems, the emerging SoC architectures integrate numerous components for the different signal processing tasks. SoC community is exploring 3D technology for the next generation of large SoC with 3D NoC. 3D design technology resolves the vertical inter-layer connection issue by TSVs. However, TSVs occupy significant silicon estate which limits the inter-layer links of the 3D NoC. Therefore, the task mapping on 3D NoC must be judicious in large SoC design. In this paper, we propose a partition algorithm for the task mapping with TSV minimization in SoC architecture. This algorithm contains divergence stage and convergence stage. Our algorithm supplies multi-way min-cut partitioning to gradually divide a given design layer by layer in the divergence stage in order to get an initial solution, then this solution is refined in convergence stage. The experiments show that our proposed algorithm performs a better capacity in the partitioning of the signal processing application.