Design of Power Efficient FPGA based Hardware Accelerators for Financial Applications

被引：0

作者：

Hegner, Jonas Stenbaek ^{[1
]}

Sindholt, Joakim ^{[1
]}

Nannarelli, Alberto ^{[1
]}

机构：

[1] Tech Univ Denmark, Dept Informat & Math Modelling, DK-2800 Lyngby, Denmark

来源：

2012 NORCHIP | 2012年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Using Field Programmable Gate Arrays (FPGAs) to accelerate financial derivative calculations is becoming very common. In this work, we implement an FPGA-based specific processor for European option pricing using Monte Carlo simulations, and we compare its performance and power dissipation to the execution on a CPU. The experimental results show that impressive results, in terms of speed-up and energy savings, can be obtained by using FPGA-based accelerators at expenses of a longer development time.

引用

页数：4

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