Characterization of Bulk Damage in CMOS MAPS With Deep N-Well Collecting Electrode

被引:9
|
作者
Zucca, Stefano [1 ,2 ]
Ratti, Lodovico [1 ]
Traversi, Gianluca [3 ,4 ]
Bettarini, Stefano [5 ,6 ]
Morsani, Fabio [6 ]
Rizzo, Giuliana [5 ,6 ]
Bosisio, Luciano [7 ,8 ]
Rashevskaya, Irina [7 ,8 ]
Cindro, Vladimir [9 ]
机构
[1] INFN Pavia, I-27100 Pavia, Italy
[2] Univ Pavia, Dipartimento Elettron, I-27100 Pavia, Italy
[3] Univ Bergamo, I-24044 Dalmine, BG, Italy
[4] INFN Pavia, I-24044 Dalmine, BG, Italy
[5] Univ Pisa, I-56127 Pisa, Italy
[6] INFN Pisa, I-56127 Pisa, Italy
[7] INFN Trieste, I-34127 Trieste, Italy
[8] Univ Trieste, I-34127 Trieste, Italy
[9] Jozef Stefan Inst, SI-1000 Ljubljana, Slovenia
关键词
Bulk damage; charge collection efficiency; CMOS MAPS; deep N-well sensor; ACTIVE PIXEL SENSORS; DISPLACEMENT DAMAGE; SILICON DETECTORS; RADIATION; DEVICES; DIODES;
D O I
10.1109/TNS.2012.2189017
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Monolithic active pixel sensors in CMOS technology, featuring a deep N-well as the collecting electrode (so called DNW MAPS), have been exposed to neutrons from a nuclear reactor, up to a total 1 MeV neutron equivalent fluence of about 3.7 x 10(13) cm(-2). The irradiation campaign was aimed at studying the effects of radiation induced displacement damage on the charge collection properties of the device, which was conceived for applications to charged particle tracking in high energy physics experiments. A number of different techniques, including electrical characterization of the front-end electronics and of DNW diodes, laser stimulation of the sensors and tests with Fe-55 and Sr-90 radioactive sources, has been employed for evaluating the device operation before and after irradiation. This paper discusses the measurement results and their relation with the bulk damage mechanisms underlying performance degradation in DNW MAPS.
引用
收藏
页码:900 / 908
页数:9
相关论文
共 50 条
  • [41] Towards a high performance vertex detector based on 3D integration of deep N-well MAPS
    Re, V.
    JOURNAL OF INSTRUMENTATION, 2010, 5
  • [42] A high isolation CMFB downconversion micromixer using 0.18-μm deep N-well CMOS technology
    Dept. of Communications Engineering, National Chiao Tung University, Hsin-Chu, Taiwan
    不详
    不详
    IEEE Radio Freq Integr Circuits Symp RFIC Dig Tech Pap, (619-622):
  • [43] A 65-nm CMOS P-well/Deep N-well Avalanche Photodetector for Integrated 850-nm Optical
    Pan, Quan
    Hon, Zhengxiong
    Wang, Yipeng
    Yue, C. Patrick
    2013 IEEE 10TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2013,
  • [44] Simulation Study of Single Event Effect for Different N-Well and Deep-N-Well Doping in 65nm Triple-Well CMOS Devices
    Wang, Tianqi
    Xiao, Liyi
    Huang, Qingfeng
    2012 INTERNATIONAL CONFERENCE ON OPTOELECTRONICS AND MICROELECTRONICS (ICOM), 2012, : 505 - 509
  • [45] A Simple Test Structure for Directly Extracting Substrate Network Components in Deep n-Well RF-CMOS Modeling
    Liu, Jun
    Sun, Lingling
    Lou, Liheng
    Wang, Huang
    McCorkell, Charles
    IEEE ELECTRON DEVICE LETTERS, 2009, 30 (11) : 1200 - 1202
  • [46] N-WELL AND P-WELL OPTIMIZATION FOR HIGH-SPEED N-EPITAXY CMOS CIRCUITS
    SCHWABE, U
    HERBST, H
    JACOBS, EP
    TAKACS, D
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1983, 30 (10) : 1339 - 1344
  • [47] OPTIMIZED RETROGRADE N-WELL FOR 1-MU-M CMOS TECHNOLOGY
    MARTIN, RA
    CHEN, JYT
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1986, 21 (02) : 286 - 292
  • [48] SET Response of the Selectively Implanted Deep N-Well -Comparison With Dual Well and Triple Well
    Jianguo, Hu
    Yibai, He
    Ge, Lin
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2015, 15 (03) : 370 - 375
  • [49] STUDY OF 2 mu m EPITAXIAL N-WELL CMOS TECHNOLOGY.
    Ma, Huainan
    Xu, Jiasheng
    Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors, 1987, 8 (04): : 378 - 384
  • [50] DESIGN-MODEL AND GUIDELINE FOR N-WELL GUARD RING IN EPITAXIAL CMOS
    HUANG, CY
    CHEN, MJ
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1994, 41 (10) : 1806 - 1810