STUDY OF 2 mu m EPITAXIAL N-WELL CMOS TECHNOLOGY.

被引：0
|
作者：
Ma, Huainan [1 ]
Xu, Jiasheng [1 ]
机构：
[1] Qinghua Univ, China, Qinghua Univ, China
来源：
Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors | 1987年 / 8卷 / 04期
关键词：
CMOS TECHNOLOGY - I-V CHARACTERISTICS;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：378 / 384
相关论文
共 50 条
  • [1] 1. 0- mu M N-WELL CMOS/BIPOLAR TECHNOLOGY.
    Momose, Hiroshi
    Shibata, Hideki
    Saitoh, Shinji
    Miyamoto, Jun'ichi
    Kanzaki, Kohichi
    Kohyama, Susumu
    1600, (SC-20):
  • [2] 1.0-MU-M N-WELL CMOS BIPOLAR TECHNOLOGY
    MOMOSE, H
    SHIBATA, H
    SAITOH, S
    MIYAMOTO, J
    KANZAKI, K
    KOHYAMA, S
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1985, 20 (01) : 137 - 143
  • [3] 1.0-MU-M N-WELL CMOS BIPOLAR TECHNOLOGY
    MOMOSE, H
    SHIBATA, H
    SAITOH, S
    MIYAMOTO, J
    KANZAKI, K
    KOHYAMA, S
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1985, 32 (02) : 217 - 223
  • [4] OPTIMIZED RETROGRADE N-WELL FOR 1-MU-M CMOS TECHNOLOGY
    MARTIN, RA
    CHEN, JYT
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1986, 21 (02) : 286 - 292
  • [5] PROCESS AND DEVICE PERFORMANCE OF 1-MU-M-CHANNEL N-WELL CMOS TECHNOLOGY
    YAMAGUCHI, T
    MORIMOTO, S
    KAWAMOTO, GH
    DELACY, JC
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1984, 31 (02) : 205 - 214
  • [6] LATCH-UP STUDIES IN A 0.5-MU-M GATE CMOS TECHNOLOGY WITH RETROGRADE N-WELL
    CHANG, WH
    WANG, LK
    WACHNIK, RA
    JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1987, 134 (03) : C118 - C118
  • [7] A SELF-ALIGNED 1-MU-M-CHANNEL CMOS TECHNOLOGY WITH RETROGRADE N-WELL AND THIN EPITAXY
    TAUR, Y
    HU, GJ
    DENNARD, RH
    TERMAN, LM
    TING, CY
    PETRILLO, KE
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1985, 32 (02) : 203 - 209
  • [8] A SELF-ALIGNED 1-MU-M-CHANNEL CMOS TECHNOLOGY WITH RETROGRADE N-WELL AND THIN EPITAXY
    TAUR, Y
    HU, GJ
    DENNARD, RH
    TERMAN, LM
    TING, CY
    PETRILLO, KE
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1985, 20 (01) : 123 - 129
  • [9] EPITAXIAL LAYER ENHANCEMENT OF N-WELL GUARD RINGS FOR CMOS CIRCUITS
    TROUTMAN, RR
    IEEE ELECTRON DEVICE LETTERS, 1983, 4 (12) : 438 - 440
  • [10] PERFORMANCE OF A SCALED SI GATE N-WELL CMOS TECHNOLOGY
    ZIMMER, G
    FIEDLER, H
    HOEFFLINGER, B
    NEUBERT, E
    VOGT, H
    ELECTRONICS LETTERS, 1981, 17 (18) : 666 - 667
12345