LATCH-UP STUDIES IN A 0.5-MU-M GATE CMOS TECHNOLOGY WITH RETROGRADE N-WELL

被引：0
|
作者：
CHANG, WH [1 ]
WANG, LK [1 ]
WACHNIK, RA [1 ]
机构：
[1] IBM CORP,THOMAS J WATSON RES CTR,YORKTOWN HTS,NY 10598
来源：
JOURNAL OF THE ELECTROCHEMICAL SOCIETY | 1987年 / 134卷 / 03期
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D O I：
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中图分类号：
O646 [电化学、电解、磁化学];
学科分类号：
081704 ;
摘要：
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页码：C118 / C118
页数：1
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