Low Power Dual Edge Triggered Flip Flop using Multi Threshold CMOS

In this work, a low power dual edge triggered flip flop design using multi threshold CMOS is proposed. Proposed Flip-Flop (FF) has three new feature points. First point, the pulse generation control logic is designed with EXOR gate and inverter chain which reduces the complexity and extra switching in pulse generator circuit. Second point, signal feed through technique with some modification is devised to speed up the charging and discharging along the critical path only when needed. Third point, multi-threshold CMOS technique is also applied to get low power dissipation. As a result, no. of transistors in pulse-generation circuit has been reduced for power and area saving. Various post layout simulation results based on CMOS 90-nm technology reveal that the proposed design features the best power-delay product performance in all FF designs under comparison.