Back-gate forward bias method for low-voltage CMOS digital circuits

被引：33
|
作者：
Chen, MJ
Ho, JS
Huang, TH
Yang, CH
Jou, YN
Wu, T
机构：
[1] NATL CHIAO TUNG UNIV,INST ELECTR,HSINCHU 300,TAIWAN
[2] ITRI,ELECT RES & SERV ORG,MIXED MODE INTEGRATED CIRCUITS DEPT,HSINCHU 300,TAIWAN
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 1996年 / 43卷 / 06期
关键词：
D O I：
10.1109/16.502122
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The back-gate forward bias method suitable for present standard hulk CMOS processes has been promoted for low-voltage digital circuit application, A CMOS inverter employing the method has experimentally exhibited the ability of electrically adjusting the transition region of the de voltage transfer characteristics. Transient measurement has further shown that the inverter with a back-gate forward bias of 0.4 V can operate at low supply voltages down to 0.6 V without significant loss in switching speed, Guidelines for ensuring proper implementation of tile method in a bulk CMOS process has been set up against latch-up, parasitic bipolar, impact ionization, and stand-by current, Following these guidelines, a cost-effective low-power, low-voltage, high-density mixed-mode CMOS analog/digital integrated circuits chip with both reasonable speed and improved precision has been projected for the first time.
引用
收藏
页码：904 / 910
页数：7
相关论文
共 50 条
  • [1] Back-gate forward bias method for low-voltage CMOS digital circuits
    Natl Chiao-Tung Univ, Hsinchu, Taiwan
    [J]. IEEE Trans Electron Devices, 6 (904-910):
  • [2] Back gate bias method of threshold voltage control for the design of low voltage CMOS ternary logic circuits
    Srivastava, A
    [J]. MICROELECTRONICS RELIABILITY, 2000, 40 (12) : 2107 - 2110
  • [3] Phase noise in a back-gate biased low-voltage VCO
    Kazemeini, MH
    Deen, MJ
    Naseh, S
    [J]. PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I: ANALOG CIRCUITS AND SIGNAL PROCESSING, 2003, : 701 - 704
  • [4] A low-voltage wide-input CMOS comparator for sensor application using back-gate technique
    Hung, YC
    Liu, BD
    [J]. BIOSENSORS & BIOELECTRONICS, 2004, 20 (01): : 53 - 59
  • [5] LOW-VOLTAGE SCALED CMOS AND BICMOS DIGITAL CIRCUITS
    BELLAOUAR, A
    EMBABI, SHK
    ELMASRY, MI
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1992, 39 (04) : 1005 - 1009
  • [6] Dynamic back bias CMOS driver for low-voltage applications
    Moisiadis, Y
    Bouras, I
    Arapoyanni, A
    [J]. ELECTRONICS LETTERS, 2000, 36 (02) : 135 - 136
  • [7] Process compensation techniques for low-voltage CMOS digital circuits
    Graduate School of Information Science and Technology, Hokkaido University, kita 14, nishi 9, kita-ku, Sapporo 060-0814, Japan
    不详
    [J]. Kyokai Joho Imeji Zasshi, 2009, 11 (1667-1670):
  • [8] Compact low-voltage self-calibrating digital floating-gate CMOS logic circuits
    Ytterdal, T
    Aunet, S
    [J]. 2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V, PROCEEDINGS, 2002, : 393 - 396
  • [9] A Forward Body Bias Generator for Digital CMOS Circuits with Supply Voltage Scaling
    Meijer, Maurice
    de Gyvez, Jose Pineda
    Kup, Ben
    van Uden, Bert
    Bastiaansen, Peter
    Lammers, Marco
    Vertregt, Maarten
    [J]. 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 2482 - 2485
  • [10] LOW-VOLTAGE CMOS ANALOG CIRCUITS
    HOSTICKA, BJ
    BROCKHERDE, W
    HAMMERSCHMIDT, D
    KOKOZINSKI, R
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS, 1995, 42 (11): : 864 - 872
12345