Negative bias temperature instability in n-channel power VDMOSFETs

被引：24

作者：

Dankovic, D. ^{[1
]}

Manic, I. ^{[1
]}

Davidovic, V. ^{[1
]}

Djoric-Veljkovic, S. ^{[2
]}

Golubovic, S. ^{[1
]}

Stojadinovic, N. ^{[1
]}

机构：

[1] Univ Nis, Fac Elect Engn, Nish 18000, Serbia

[2] Univ Nis, Fac Civil Engn & Architecture, Nish 18000, Serbia

来源：

MICROELECTRONICS RELIABILITY | 2008年 / 48卷 / 8-9期

关键词：

D O I：

10.1016/j.microrel.2008.06.015

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Negative gate bias is used in some applications for faster switching off the n-channel MOS devices. It is shown in this Study that NBT stress-related instability in commercial n-channel power VDMOSFETs could be actually more serious than in corresponding p-channel devices. NBT stress is found to create equal V-T shifts in both device types, whereas the subsequent positive bias annealing results in more serious overall V-T instability in n-channel devices. The changes in the densities of stress-induced interface traps in two device types are equal as well, but significant amounts of NBT stress-induced border traps are only found in n-channel devices. All the results are discussed in terms of hydrogen reaction and diffusion model. (C) 2008 Elsevier Ltd. All rights reserved.

引用

页码：1313 / 1317

页数：5

共 50 条

[11] Negative Gate Bias TDDB evaluation of n-Channel SiC Vertical Power MOSFETs
Ganguly, Satyaki
Lichtenwalner, Daniel J.
Isaacson, Caleb
Gajewski, Donald A.
Steinmann, Philipp
Foarde, Ryan
Hull, Brett
Ryu, Sei-Hyung
Allen, Scott
Palmour, John W.
2022 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2022,
[12] Novel positive Bias Temperature Instability (PBTI) of N-channel MOSFETs with plasma nitrided oxide
Huard, V.
Guerin, C.
Parthasarthy, C.
2007 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 45TH ANNUAL, 2007, : 686 - +
[13] THRESHOLD-VOLTAGE INSTABILITY OF N-CHANNEL MOSFETS UNDER BIAS-TEMPERATURE AGING
SHIONO, N
HASHIMOTO, C
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1982, 29 (03) : 361 - 368
[14] Formation and passivation of interface traps in irradiated n-channel power VDMOSFETs during thermal annealing
Pejovic, M
Ristic, G
Jaksic, A
APPLIED SURFACE SCIENCE, 1997, 108 (01) : 141 - 148
[15] Bias Temperature Instability of 4H-SiC p- and n-Channel MOSFETs Induced by Negative Stress at 200 °C
Yang, Liao
Bai, Yun
Li, Chengzhan
Chen, Hong
Tang, Yidan
Hao, Jilong
Yang, Chengyue
Tian, Xiaoli
Lu, Jiang
Liu, Xinyu
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2022, 69 (06) : 3042 - 3046
[16] Repeating of positive and negative high electric field stress and corresponding thermal post-stress annealing of the n-channel power VDMOSFETs
Aleksic, Sanja M.
Jaksic, Aleksandar B.
Pejovic, Momcilo M.
SOLID-STATE ELECTRONICS, 2008, 52 (08) : 1197 - 1201
[17] Defect behaviors in n-channel power VDMOSFETs during HEFS and thermal post-HEFS annealing
Ristic, GS
Pejovic, MM
Jaksic, AB
APPLIED SURFACE SCIENCE, 2006, 252 (08) : 3023 - 3032
[18] Comparison between positive and negative bias stress on N-channel VDMOSFET transistors
Abboud, N.
Habch, R.
Cuminal, Y.
Foucaran, A.
Salame, C.
INTERNATIONAL JOURNAL OF STRUCTURAL INTEGRITY, 2013, 4 (02) : 267 - 274
[19] Impact of negative bias temperature instability on p-channel power VDMOSFET used in practical applications
Mitrovic, N.
Veljkovic, S.
Davidovic, V.
Djoric-Veljkovic, S.
Golubovic, S.
Zivanovic, E.
Prijic, Z.
Dankovic, D.
MICROELECTRONICS RELIABILITY, 2022, 138
[20] Modeling of Static Negative Bias Temperature Stressing in p-channel VDMOSFETs using Least Square Method
Mitrovic, Nikola
Dankovic, Danijel
Randelovic, Branislav
Prijic, Zoran
Stojadinovic, Ninoslav
INFORMACIJE MIDEM-JOURNAL OF MICROELECTRONICS ELECTRONIC COMPONENTS AND MATERIALS, 2020, 50 (03): : 205 - 214

← 1 2 3 4 5 →