Performance Improvement of Heterojunction Double Gate Drain Overlapped TFET using Gaussian Doping

被引:0
|
作者
Gupta, Sarthak [1 ]
Nigam, Kaushal [1 ]
Pandey, Sunil [1 ]
Sharma, Dheeraj [1 ]
Kondekar, P. N. [1 ]
机构
[1] Indian Inst Informat Technol Design & Mfg Jabalpu, Nanoelect & VLSI Lab, Jabalpur, India
关键词
FIELD-EFFECT TRANSISTORS; TUNNEL FET;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, for the first time, a Ge/Si heterojunction pocket doped double-gate-overlapped over drain tunnel FET (HP-DGODTFET) with Gaussian doping on drain side has been investigated for low-power and high frequency applications. The proposed device offers higher I-ON/I-OFF ratio in the order of (10(14)), steeper sub threshold swing of (14 mV/decade) and better analog/RF performance metrics using low band gap material. Further, we have analysed DC and analog/RF performance parameters for pocket doped double gate TFET (P-DGTFET), heterojunction uniform doped double gate-overlapped over drain TFET (H-DGODTFET), and heterojunction pocket doped double gate overlapped over drain TFET (HP-DGODTFET) with Gaussian doping on drain side in term of transfer characteristics, transconductance (g(m)), gate to source capacitance (C-gs), gate to drain capacitance (C-gd), cut-off frequency (f(T)). All the simulations for all the possible devices have been performed with the help of ATLAS device simulator.
引用
收藏
页数:3
相关论文
共 50 条
  • [41] Dual-Material Gate-Drain Overlapped DG-TFET Device for Low Leakage Current Design
    Sunil Kumar
    Balwant Raj
    Balwinder Raj
    Silicon, 2021, 13 : 1599 - 1607
  • [42] Improvement of electrical performance in junctionless nanowire TFET using hetero-gate-dielectric
    Rahimian, Morteza
    Fathipour, Morteza
    MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING, 2017, 63 : 142 - 152
  • [43] Dual-Material Gate-Drain Overlapped DG-TFET Device for Low Leakage Current Design
    Kumar, Sunil
    Raj, Balwant
    Raj, Balwinder
    SILICON, 2021, 13 (05) : 1599 - 1607
  • [44] Analytical Study of the Effect of Asymmetric Gate Bias on the Performance of double gate TFET
    Gupta, Parthasarathi
    Das, Jayita
    Burman, Debasree
    Brahma, Madhuchhanda
    Rahaman, Hafizur
    Dasgupta, Parthasarathi
    PROCEEDINGS OF THE 2012 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, DEVICES AND INTELLIGENT SYSTEMS (CODLS), 2012, : 145 - 148
  • [45] Performance Enhancement of Novel InAs/Si Hetero Double-Gate Tunnel FET Using Gaussian Doping
    Ahish, Shylendra
    Sharma, Dheeraj
    Kumar, Yernad Balachandra Nithin
    Vasantha, Moodabettu Harishchandra
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (01) : 288 - 295
  • [46] Analytical modelling for surface potential of dual material gate overlapped-on-drain TFET(DM-DMG-TFET) for label-free biosensing application
    Reddy, Nelaturi Nagendra
    Panda, Deepak Kumar
    Saha, Rajesh
    AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2022, 151
  • [47] Effect of Drain Doping and Temperature Variation on the Performance of Heterojunction Double Gate Tunnel Field Effect Transistor from a 2D ATLAS Simulation
    Ahish, S.
    Sharma, Dheeraj
    Kumar, Y. B. N.
    Vasantha, M. H.
    JOURNAL OF NANOELECTRONICS AND OPTOELECTRONICS, 2017, 12 (02) : 162 - 170
  • [48] Insights into temperature influence on analog/RF and linearity performance of a Si/Ge heterojunction asymmetric double gate dopingless TFET
    Sharma, Suruchi
    Basu, Rikmantra
    Kaur, Baljit
    APPLIED PHYSICS A-MATERIALS SCIENCE & PROCESSING, 2021, 127 (05):
  • [49] Insights into temperature influence on analog/RF and linearity performance of a Si/Ge heterojunction asymmetric double gate dopingless TFET
    Suruchi Sharma
    Rikmantra Basu
    Baljit Kaur
    Applied Physics A, 2021, 127
  • [50] Impact of Drain Thickness Asymmetry on DC and Analog/RF Performance of an n-type SiGe/Si Double Gate TFET
    Panda, Shwetapadma
    Dash, Sidhartha
    SILICON, 2023, 15 (05) : 2173 - 2183