RTL level trace signal selection and coverage estimation during post-silicon validation

被引:0
|
作者
Kumar, Binod [1 ]
Basu, Kanad [2 ]
Fujita, Masahiro [3 ]
Singh, Virendra [1 ]
机构
[1] Indian Inst Technol, Bombay, Maharashtra, India
[2] NYU, New York, NY 10003 USA
[3] Univ Tokyo, Tokyo, Japan
关键词
RTL signal selection; Restorability; Post-silicon validation; Design bugs; Assertions;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Trace buffers play a crucial role in curbing the obstacle of limited observability of internal states for error localization during post-silicon stage. Given the constraint of area over-head, selecting appropriate signals which are to be stored in the trace buffers is of paramount importance for the overall success of this observability enhancement mechanism. This paper proposes a register-transfer level trace signal selection methodology which uses assertions generated during pre-silicon design verification. The enlarged quantity of restored signal states in conjunction with the traced states help to estimate the coverage of particular events during post-silicon validation; thus, acting as a suitable alternative to synthesizing coverage monitors. Experimental results on opencore benchmark circuits indicate that the proposed methodology performs better than existing trace signal selection techniques, which focus on maximization of restoration of untraced signals from the traced ones.
引用
收藏
页码:59 / 66
页数:8
相关论文
共 50 条
  • [31] Efficient Selection of Trace and Scan Signals for Post-Silicon Debug
    Rahmani, Kamran
    Proch, Sudhi
    Mishra, Prabhat
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 24 (01) : 313 - 323
  • [32] Did We Test Enough? Functional Coverage for Post-Silicon Validation
    Pointner, Sebastian
    Wille, Robert
    [J]. 2019 IEEE INTERNATIONAL TEST CONFERENCE IN ASIA (ITC-ASIA 2019), 2019, : 31 - 36
  • [33] On bypassing blocking bugs during post-silicon validation
    Daoud, Ehab Anis
    Nicolici, Nicola
    [J]. PROCEEDINGS OF THE 13TH IEEE EUROPEAN TEST SYMPOSIUM: ETS 2008, 2008, : 69 - 74
  • [34] Automated Selection of Assertions for Bit-Flip Detection During Post-Silicon Validation
    Taatizadeh, Pouya
    Nicolici, Nicola
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2016, 35 (12) : 2118 - 2130
  • [35] Extending Trace History Through Tapered Summaries in Post-silicon Validation
    Chandran, Sandeep
    Panda, Preeti Ranjan
    Sarangi, Smruti R.
    Chauhan, Deepak
    Kumar, Sharad
    [J]. 2016 21ST ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2016, : 737 - 742
  • [36] Improving Post-silicon Error Detection with Topological Selection of Trace Signals
    Kumar, Binod
    Basu, Kanad
    Jindal, Ankit
    Fujita, Masahiro
    Singh, Virendra
    [J]. 2017 IFIP/IEEE INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC), 2017, : 172 - 177
  • [37] Enhanced Algorithm of Combining Trace and Scan Signals in Post-Silicon Validation
    Han, Kihyuk
    Yang, Joon-Sung
    Abraham, Jacob A.
    [J]. 2013 IEEE 31ST VLSI TEST SYMPOSIUM (VTS), 2013,
  • [38] Layout-aware Selection of Trace Signals for Post-Silicon Debug
    Thakyal, Prateek
    Mishra, Prabhat
    [J]. 2014 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2014, : 327 - 332
  • [39] Construction of Coverage Data for Post-Silicon Validation Using Big Data Techniques
    El Mandouh, Eman
    Gamal, A.
    Khaled, A.
    Ibrahim, T.
    Wassal, Amr G.
    Hemayed, Elsayed
    [J]. 2017 24TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2017, : 46 - 49
  • [40] Can't See the Forest for the Trees: State Restoration's Limitations in Post-silicon Trace Signal Selection
    Ma, Sai
    Pal, Debjit
    Jiang, Rui
    Ray, Sandip
    Vasudevan, Shobha
    [J]. 2015 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 2015, : 1 - 8