Modeling and electrical analysis of seamless high off-chip connectivity (SHOCC) interconnects

Scaling down on-chip interconnect cross-sectional dimensions results not only in higher circuit wiring density, but also in the long lossy line problem, wherein the long lines become highly resistive and have unacceptable delays. One possible solution to the problem of long lossy lines is to transfer these lines off-chip using Seamless High Off-Chip (SHOCC) technology concepts, including dense chip I/O interconnects to an interposing substrate. In this work, we modeled and studied the electrical performance of SHOCC signal lines. The performance of SHOCC interconnects, including suitable drivers, on-chip sections, solder bumps, and off-chip sections, was compared with that of typical on-chip interconnects. Modeling and simulation results, along with recommendations with regards to driver sizes and the type of interconnect that should be used, are presented. It is shown that, even with the overhead of going from chip to substrate and back; SHOCC interconnects outperform on-chip interconnects of reasonable cross section when the interconnect length is over .65 cm, no matter how large an on-chip driver is used. Even shorter SHOCC interconnects outperform those on-chip when driven by equal-sized drivers.