共 50 条
- [43] Modification on the IPEG algorithm for constructing LDPC codes with low error floor 2007 IEEE 65TH VEHICULAR TECHNOLOGY CONFERENCE, VOLS 1-6, 2007, : 2215 - 2217
- [44] Boosting Learning for LDPC Codes to Improve the Error-Floor Performance ADVANCES IN NEURAL INFORMATION PROCESSING SYSTEMS 36 (NEURIPS 2023), 2023,
- [45] Construction of Short-Length LDPC Codes with Low Error Floor 2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4, 2008, : 1818 - +
- [46] An Efficient Post Processing Scheme to Lower the Error Floor of LDPC Decoders 2017 17TH IEEE INTERNATIONAL CONFERENCE ON COMMUNICATION TECHNOLOGY (ICCT 2017), 2017, : 122 - 126
- [47] Error floor behavior study of LDPC codes for concatenated codes design SECOND INTERNATIONAL CONFERENCE ON SPACE INFORMATION TECHNOLOGY, PTS 1-3, 2007, 6795
- [48] Serial Concatenation of Reed Muller and LDPC Codes with Low Error Floor 2017 55TH ANNUAL ALLERTON CONFERENCE ON COMMUNICATION, CONTROL, AND COMPUTING (ALLERTON), 2017, : 688 - 693
- [49] Block interleaving algorithm for construction of low error floor LDPC codes Qinghua Daxue Xuebao/Journal of Tsinghua University, 2010, 50 (01): : 153 - 155