Compact Modeling for Gate-All-Around Nanowire Tunneling FETs (GAA NW-tFETs)

A compact model for gate-all-around (GAA) nanowire tunneling FETs (NW-tFETs) is developed based on ballistic transport and charge balancing approaches. To account for the carrier injection to the channel from source/drain (S/D) regions for NW FETs, the density-of-states (DOS) charge, which results in the so-called quantum capacitance, is introduced and augmented to include tunneling phenomenon. A complete large-signal equivalent circuit is proposed for the first time, including the doping effects in S/D regions. Preliminary results from comparison of model prediction and numerical device simulation show the correctness of the modeling methodology.