共 50 条
- [1] Compact Modeling for Gate-All-Around Nanowire Tunneling FETs (GAA NW-tFETs) [J]. 2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT-2012), 2012, : 819 - 822
- [6] Gate-All-Around Silicon Nanowire Devices: Are these the Future of CMOS? [J]. SIGE, GE, AND RELATED COMPOUNDS 3: MATERIALS, PROCESSING, AND DEVICES, 2008, 16 (10): : 729 - 729
- [8] Gate-all-around twin silicon nanowire SONOS memory [J]. 2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2007, : 142 - +
- [9] Structure effects in the gate-all-around silicon nanowire MOSFETs [J]. EDSSC: 2007 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, VOLS 1 AND 2, PROCEEDINGS, 2007, : 129 - 132
- [10] Modeling and analysis of gate-all-around silicon nanowire FET [J]. MICROELECTRONICS RELIABILITY, 2014, 54 (6-7) : 1103 - 1108