A 210-GHz Amplifier in 40-nm Digital CMOS Technology

被引：32

作者：

Ko, Chun-Lin ^{[1
,2
,3
]}

Li, Chun-Hsing ^{[1
,2
]}

Kuo, Chien-Nan ^{[1
,2
]}

Kuo, Ming-Ching ^{[4
]}

Chang, Da-Chiang ^{[3
]}

机构：

[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan

[2] Natl Chiao Tung Univ, Inst Elect, Hsinchu 300, Taiwan

[3] Natl Chip Implementat Ctr CIC, Natl Appl Res Labs, Hsinchu 300, Taiwan

[4] Ind Technol Res Inst, Informat & Commun Res Lab ICL, Hsinchu 310, Taiwan

来源：

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES | 2013年 / 61卷 / 06期

关键词：

Amplifier; maximum gain; shunt stub matching; transmission line; ALGORITHMIC DESIGN; POWER-AMPLIFIER; GHZ; CIRCUITS;

D O I：

10.1109/TMTT.2013.2260767

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a 210-GHz amplifier design in 40-nm digital bulk CMOS technology. The theoretical maximum voltage gain that an amplifier can achieve and the loss of a matching network are derived for the optimization of a few hundred gigahertz amplifiers. Accordingly, the bias and size of transistors, circuit topology, and inter-stage coupling method can be determined methodically to maximize the amplifier gain. The measured results show that the amplifier exhibits a peak power gain of 10.5 dB at 213.5 GHz and an estimated 3-dB bandwidth of 13 GHz. The power consumption is only 42.3 mW under a 0.8-V supply. To the best of the authors' knowledge, this work demonstrates the CMOS amplifier with highest operation frequency reported thus far.

引用

页码：2438 / 2446

页数：9

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