Analysis of USJ formation with combined RTA/laser annealing conditions for 28 nm high-k/metal gate CMOS technology using advanced TCAD for process and device simulation

被引：2

作者：

Bazizi, E. M. ^{[1
]}

Zaka, A. ^{[1
]}

Benistant, F. ^{[2
]}

机构：

[1] GLOBALFOUNDRIES, Wilschdorfer Landstr 101, D-01109 Dresden, Germany

[2] GLOBALFOUNDRIES, Singapore 738406, Singapore

来源：

SOLID-STATE ELECTRONICS | 2013年 / 83卷

关键词：

28 nm HKMG; Spike; Laser; Implantation; Activation; Simulation; DEFECT EVOLUTION; DIFFUSION; PERFORMANCE; BORON;

D O I：

10.1016/j.sse.2013.01.023

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

TCAD process and device simulations are used to gain physical understanding for the integration of laser-annealed junctions into a 28 nm high-k/metal gate first process flow. Spike-RTA (Rapid Thermal Annealing) scaling used for transient enhanced diffusion (TED) suppression and shallow extension formation is investigated. In order to overcome the performance loss due to a reduced RTA, laser anneal (Isa) is introduced after Spike-RTA to form highly activated and ultra shallow junctions (USJs). In this work, the impact of different annealing conditions on the performance of NMOS and PMOS devices is investigated in terms of V-th and I-on/I-off, considering lateral dopant diffusion and activation. (c) 2013 Elsevier Ltd. All rights reserved.

引用

页码：61 / 65

页数：5

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