A unified compact model of the gate oxide reliability for complete circuit level analysis

被引：1

作者：

Lee, Chi-Hwan ^{[1
]}

Yang, Gi-Young ^{[1
]}

Park, Jin-Kyu ^{[1
]}

Park, Young-Kwan ^{[1
]}

Kim, Hyung-Wook ^{[2
]}

Park, Donggun ^{[3
]}

Yoo, Moon-Hyun ^{[1
]}

机构：

[1] Saumsung Elect Co Ltd, Semicond R&D Ctr, CAE Team, San 16 Banwol Dong, Hwasung City 445701, Gyunggi Do, South Korea

[2] Saumsung Elect Co Ltd, Semicond R&D Ctr, Quality Assurance Team, Hwasung City 445701, Gyunggi Do, South Korea

[3] Saumsung Elect Co Ltd, Semicond R&D Ctr, Technol Dev Team, Hwasung City 445701, Gyunggi Do, South Korea

来源：

2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2 | 2007年

关键词：

D O I：

10.1109/IEDM.2007.4418997

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

A unified compact model to predict the performance degradation of a circuit due to the electrical gate oxide stress is developed and verified by experimental results. Hot carrier injection (HCI), off-state (OS), and Fowler-Nordheim (FN) degradations can be described by a single formula which models the trap generation over the stress time and voltage. With the proposed model, the propagation delay (tPD) degradation of a ring oscillator is reproduced with the accuracy of more than 90%. It is found that OS plays major role in the tPD degradation rather than HCI, while the component ratio of HCI is getting larger as the frequency increases.

引用

页码：549 / +

页数：3

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