Advanced Flip-Chip Package Solution for 28nm Si Node and Beyond

被引：0
|
作者：
Liu, C. S. [1 ]
Chen, C. S. [1 ]
Lee, C. H. [1 ]
Tsai, H. Y. [1 ]
Pu, H. P. [1 ]
Cheng, M. D. [1 ]
Kuo, T. H. [1 ]
Chen, H. W. [1 ]
Wu, C. Y. [1 ]
Lii, M. J. [1 ]
Yu, Doug C. H. [1 ]
机构：
[1] Taiwan Semicond Mfg Co Ltd, Res & Dev, Hsinchu 30077, Taiwan
来源：
2012 IEEE 62ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) | 2012年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Next generation flip chip package with <100um fine bump pitch is developed in a cost effective Bump-on-Trace (BOT) package structure for 28nm Si technology node. This is foreseen to be a mainstream for mobile applications in next generations. The key challenges of this new technology include warpage control of molded underfill (MUF) for < 4 mils of thin die, packaging yield due to finer pitch of bumping/substrate design and thermal/mechanical effect on chip-package-interaction (CPI) [1-2]. CPI due to the use of fragile extreme low-k (ELK) dielectric material in the back-end-of-line (BEOL) layers has been fully characterized. The well-integrated Si/bump/package processes enable reliable CPI and assembly yield. An aggressive and reliable Si/bump/package design and CPI approaches are also discussed.
引用
收藏
页码：436 / 438
页数：3
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