Low-Leakage Hybrid FinFET SRAM Cell with Asymmetrical Gate Overlap/Underlap Bitline Access Transistors for Enhanced Read Data Stability

The degraded read data stability and write ability of SRAM cells have become primary design concerns with CMOS technology scaling into the sub-22nm channel lengths. A new six-FinFET SRAM cell with asymmetrical bitline access transistors is proposed in this paper for enhancing the read data stability and suppressing the leakage power consumption in memory circuits. The bitline access transistor channel is underlapped on one side while overlapped by the gate terminal on the opposite side of the transistor. The asymmetrical bitline access transistors are weakened during read operations and strengthened during write operations as the direction of current flow is reversed. With the proposed asymmetrical six-FinFET SRAM cell, the read data stability is enhanced by up to 62% and the leakage power consumption is reduced by up to 49.3%, while maintaining similar write margin, cell layout area, read delay, and write delay as compared to a previously published asymmetrical six-FinFET SRAM cell in a 15nm FinFET technology.