High-Speed and Low-Leakage FinFET SRAM Cell with Enhanced Read and Write Voltage Margins

被引：0
|
作者：
Salahuddin, Shairfe Muhammad [1 ]
Kursun, Volkan [1 ]
机构：
[1] Hong Kong Univ Sci & Technol, Dept Elect & Comp Engn, Kowloon, Hong Kong, Peoples R China
来源：
2014 14TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC) | 2014年
关键词：
HIGHER INTEGRATION DENSITY; STABILITY;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new single-ended read asymmetrical SRAM cell with underlap engineered symmetrical FinFETs is proposed in this paper for achieving stronger data stability, enhanced write ability, and suppressed leakage power consumption as compared to previously published six-FinFET memory circuits. With the new SRAM cell, the read data stability, read speed, write voltage margin, and write speed are enhanced by up to 2.7x, 57.6%, 25.5%, and 20.1% while the leakage power consumption is reduced by up to 69.8% without degrading the memory integration density as compared to the previously published six-FinFET SRAM cells in a 15nm FinFET technology.
引用
收藏
页码：312 / 315
页数：4
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