A low power, high speed FinFET based 6T SRAM cell with enhanced write ability and read stability

被引：0

作者：

Premavathi, Rahaprian Mudiarasan ^{[1
]}

Tong, Qiang ^{[1
]}

Choi, Ken ^{[1
]}

Lee, Yunsik ^{[2
]}

机构：

[1] IIT, Dept Elect & Comp Engn, Chicago, IL 60616 USA

[2] UNIST, Sch ECE, Ulsan, South Korea

来源：

2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) | 2016年

关键词：

Read SNM free; Power Delay Product; Write Trip Point;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a FinFET based 6T SRAM cell, with separate read access path and write path, designed by combining the advantages of conventional single ended 5T and the conventional 8T SRAM cells. The proposed SRAM cell achieves 70% and 55% of write performance improvement in terms of Power delay product (PDP) than 8T (also conventional 6T) and 5T SRAM cells respectively. Proposed cell achieves 78% of hold 1 and 40% of hold 0 static power reduction than the conventional 5T, 6T and 8T cells. The proposed cell is read SNM free and also achieves better hold SNM and write ability than 5T and 8T SRAM cells.

引用

页码：311 / 312

页数：2

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