Efficient high-speed/low-power line-based architecture for two-dimensional discrete wavelet transform using lifting scheme

被引:28
|
作者
Xiong, CY [1 ]
Tian, JW
Liu, JA
机构
[1] Huazhong Univ Sci & Technol, Educ Minist Image Proc & Intelligent Control, Key Lab, Inst Pattern Recognit & Artificial Intelligence, Wuhan 430074, Peoples R China
[2] S Ctr Univ Nationalities, Coll Elect Informat Engn, Wuhan 430074, Peoples R China
关键词
discrete wavelet transform (DWT); highspeed/lower power; lifting scheme; pipelined;
D O I
10.1109/TCSVT.2005.860121
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Efficient line-based architectures for two-dimensional discrete wavelet transform (2-D DWT) are presented in this paper. We first present a four-input/four-output architecture for direct 2-D DWT that 1-level decomposition of a N x N image could be performed in approximately N-2/4 intra-working clock cycles (ccs), where the parallelism among four subbands transforms in lifting-based 2-D DWT is explored. By using this four-input/four-output architecture, we propose a novel pipelined architecture for multilevel 2-D DWT that can perform a complete dyadic decomposition of N x N image in approximately N-2/4 ccs. Performance analysis and comparison results demonstrate that, the proposed architectures have faster throughput rate and good performance in terms of production of throughput rate and hardware cost, as well as hardware utilization. The proposed pipelined architecture could be an efficient alternative for high-speed and/or low-power applications.
引用
收藏
页码:309 / 316
页数:8
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