A 1.5V 8-bit low-power self-calibrating high-speed folding ADC

被引：0

作者：

Movahedian, H ^{[1
]}

Bakhtiar, S ^{[1
]}

机构：

[1] Sharif Univ Technol, Dept Elect Engn, Tehran, Iran

来源：

2005 PhD Research in Microelectronics and Electronics, Vols 1 and 2, Proceedings | 2005年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An 8-bit High-speed folding/interpolating ADC is presented. Designed in 0.18 mu m CMOS technology, the ADC dissipates only 50mW from a single 1.5V supply. A novel technique based on using both N and P folding cells is used to widen the input range and a self-calibration technique based on using Trimmable MOSFETs is employed to improve the static and dynamic performance.

引用

页码：33 / 36

页数：4

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