Silicon evaluation of logic proximity bridge patterns

被引：4
|
作者：
Tran, Eric N.
Kasulasrinivas, Vishwashanth
Chakravarty, Sreejit
机构：
来源：
24TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 2006年
关键词：
D O I：
10.1109/VTS.2006.82
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Logic Proximity Bridge (LPB) patterns were proposed as an alternative to realistic-bridge and n-detect patterns based on simulation studies. Here, silicon evaluation of logic proximity bridge patterns, on a mobile chipset product, is presented. Results show these patterns to significantly increase the class scan fallout above and beyond stuck-at patterns, consisting of single load and multi-load patterns, with very high stuck-at fault coverage. In addition it points to the usefulness of generating ATPG patterns using multiple fault models, LPB faults being one of them.
引用
收藏
页码：78 / 83
页数：6
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